Updating CModel kernel name.

Author: Virat Agarwal

host/README.md

@@ -26,7 +26,7 @@ Example        | Description           | Key Concepts / Keywords
 [host_memory_simple/][]|This is simple host memory example to describe how a user kernel can access the host memory. The host memory allocation is done through the host code. The kernel reads data from host memory and writes result to host memory.|__Key__ __Concepts__<br> - host memory<br> - address translation unit<br>__Keywords__<br> - XCL_MEM_EXT_HOST_ONLY<br> - HOST[0]
 [iops_test/][]|This is simple test design to measure Input/Output Operations per second. In this design, a simple kernel is enqueued many times and measuring overall IOPS.|__Key__ __Concepts__<br> - Input/Output Operations per second<br>__Keywords__<br> - [CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optimizingperformance.html#nzy1504034306881)
 [mult_compute_units/][]|This is simple Example of Multiple Compute units to showcase how a single kernel can be instantiated into Multiple compute units. Host code will show how to use multiple compute units and run them concurrently.|__Key__ __Concepts__<br> - [Multiple Compute Units](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#dqz1555367565037)<br>__Keywords__<br> - [nk](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/vitiscommandcompiler.html#clt1568640709907__section_wtp_zvm_1jb)
-[multiple_cus_asymmetrical/][]|This is simple example of vector addition to demonstrate how to connect each compute unit to different banks and how to use these compute units in host applications|__Key__ __Concepts__<br> - [Multiple Compute Units](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#dqz1555367565037)<br>
+[multiple_cus_asymmetrical/][]|This is simple example of vector addition to demonstrate how to connect each compute unit to different banks and how to use these compute units in host applications|__Key__ __Concepts__<br> - [Multiple Compute Units](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#dqz1555367565037)<br> - [Task Level Parallelism](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optimizingperformance.html#cvc1523913889499)<br>
 [overlap/][]|This examples demonstrates techniques that allow user to overlap Host(CPU) and FPGA computation in an application. It will cover asynchronous operations and event object.|__Key__ __Concepts__<br> - OpenCL Host API<br> - [Synchronize Host and FPGA](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#usz1524526733752)<br> - [Asynchronous Processing](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#usz1524526733752)<br> - [Events](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optimizingperformance.html#bsa1504034305860)<br> - [Asynchronous memcpy](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#usz1524526733752)<br>__Keywords__<br> - [cl_event](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#usz1524526733752)<br> - [cl::CommandQueue](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#llr1524522915783)<br> - [CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optimizingperformance.html#nzy1504034306881)<br> - [enqueueMigrateMemObjects](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/opencl_programming.html#xio1524524087132)
 [p2p_bandwidth/][]|This is simple example to test data transfer between SSD and FPGA.|__Key__ __Concepts__<br> - [P2P](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/Chunk938767849.html#qex1558551641915)<br> - SmartSSD<br> - XDMA<br>__Keywords__<br> - XCL_MEM_EXT_P2P_BUFFER<br> - pread<br> - pwrite
 [p2p_fpga2fpga/][]|This is simple example to explain P2P transfer between two FPGA devices.|__Key__ __Concepts__<br> - [P2P](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/Chunk938767849.html#qex1558551641915)<br> - Multi-FPGA Execution<br> - XDMA<br>__Keywords__<br> - XCL_MEM_EXT_P2P_BUFFER

host/multiple_cus_asymmetrical/README.rst

@@ -90,4 +90,4 @@ The kernel object which is created above is very specific to ``vadd_1``
 compute unit. Using this Kernel Object, host can directly access to this
 fix compute unit.
 
-For more comprehensive documentation, `click here <http://xilinx.github.io/Vitis_Accel_Examples>`__.
+For more comprehensive documentation, `click here <http://xilinx.github.io/Vitis_Accel_Examples>`__.

rtl_kernels/rtl_vadd/README.rst

@@ -33,7 +33,7 @@ Application code is located in the src directory. Accelerator binary files will
    src/krnl_vadd/hdl/krnl_vadd_rtl_counter.sv
    src/krnl_vadd/hdl/krnl_vadd_rtl_int.sv
    src/krnl_vadd/package_kernel.tcl
-   src/krnl_vadd/vadd_CModel.cpp
+   src/krnl_vadd/vadd_cmodel.cpp
    
 COMMAND LINE ARGUMENTS
 ----------------------

rtl_kernels/rtl_vadd/src/krnl_vadd/gen_xo.tcl

@@ -33,4 +33,4 @@ if {[file exists "${xoname}"]} {
     file delete -force "${xoname}"
 }
 
-package_xo -xo_path ${xoname} -kernel_name krnl_vadd_rtl -ip_directory ./packaged_kernel_${suffix} -kernel_files src/krnl_vadd/vadd_CModel.cpp
+package_xo -xo_path ${xoname} -kernel_name krnl_vadd_rtl -ip_directory ./packaged_kernel_${suffix} -kernel_files src/krnl_vadd/vadd_cmodel.cpp

rtl_kernels/rtl_vadd/src/krnl_vadd/vadd_CModel.cpp renamed to rtl_kernels/rtl_vadd/src/krnl_vadd/vadd_cmodel.cpp

@@ -42,6 +42,11 @@ extern "C" {
 */
 
 void krnl_vadd_rtl(uint32_t* a, uint32_t* b, uint32_t* c, ap_uint<32> length_r) {
+#pragma HLS INTERFACE m_axi port = a bundle = gmem
+#pragma HLS INTERFACE m_axi port = b bundle = gmem
+#pragma HLS INTERFACE m_axi port = c bundle = gmem
+#pragma HLS INTERFACE ap_ctrl_hs port = return
+
     for (int i = 0; i < length_r; i++) c[i] = a[i] + b[i];
 }
 }