Disabling AML for u25 and replacing bank assignments with DDRs

virata-xilinx · virata-xilinx · commit d3dd402d2ac8 · 2020-10-16T00:30:08.000+05:30
diff --git a/library_examples/anti_money_laundering/Makefile b/library_examples/anti_money_laundering/Makefile
@@ -138,6 +138,9 @@ $(EMCONFIG_DIR)/emconfig.json:
 
 ############################## Setting Essential Checks and Running Rules ##############################
 run: all
+ifeq ($(findstring _u25_, $(DEVICE)), _u25_)
+$(error This example is not supported for $(DEVICE))
+endif
 ifeq ($(findstring u50, $(DEVICE)), u50)
 $(error This example is not supported for $(DEVICE))
 endif
diff --git a/library_examples/anti_money_laundering/README.rst b/library_examples/anti_money_laundering/README.rst
@@ -10,6 +10,7 @@ Platforms containing following strings in their names are not supported for this
 
 ::
 
+   _u25_
    u50
    zc
    vck
diff --git a/library_examples/anti_money_laundering/aml.ini b/library_examples/anti_money_laundering/aml.ini
@@ -1,21 +1,21 @@
 [connectivity]
 sp=fuzzy_kernel_1_1.buf_in:PLRAM[0]
-sp=fuzzy_kernel_1_1.csv_part0:bank1
-sp=fuzzy_kernel_1_1.csv_part1:bank1
-sp=fuzzy_kernel_1_1.csv_part2:bank1
-sp=fuzzy_kernel_1_1.csv_part3:bank1
-sp=fuzzy_kernel_1_1.csv_part4:bank1
-sp=fuzzy_kernel_1_1.csv_part5:bank1
-sp=fuzzy_kernel_1_1.csv_part6:bank1
-sp=fuzzy_kernel_1_1.csv_part7:bank1
+sp=fuzzy_kernel_1_1.csv_part0:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part1:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part2:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part3:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part4:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part5:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part6:DDR[1]
+sp=fuzzy_kernel_1_1.csv_part7:DDR[1]
 sp=fuzzy_kernel_1_1.buf_out:PLRAM[0]
 sp=fuzzy_kernel_2_1.buf_in:PLRAM[1]
-sp=fuzzy_kernel_2_1.csv_part0:bank2
-sp=fuzzy_kernel_2_1.csv_part1:bank2
-sp=fuzzy_kernel_2_1.csv_part2:bank2
-sp=fuzzy_kernel_2_1.csv_part3:bank2
-sp=fuzzy_kernel_2_1.csv_part4:bank2
-sp=fuzzy_kernel_2_1.csv_part5:bank2
-sp=fuzzy_kernel_2_1.csv_part6:bank2
-sp=fuzzy_kernel_2_1.csv_part7:bank2
+sp=fuzzy_kernel_2_1.csv_part0:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part1:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part2:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part3:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part4:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part5:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part6:DDR[2]
+sp=fuzzy_kernel_2_1.csv_part7:DDR[2]
 sp=fuzzy_kernel_2_1.buf_out:PLRAM[1]
diff --git a/library_examples/anti_money_laundering/description.json b/library_examples/anti_money_laundering/description.json
@@ -10,6 +10,7 @@
         "aws"
     ],
     "platform_blacklist": [
+        "_u25_",
         "u50",
         "zc",
         "vck"
@@ -62,35 +63,35 @@
                                 },
                                 {
                                     "name": "csv_part0", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                     "name": "csv_part1", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                     "name": "csv_part2", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                     "name": "csv_part3", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                     "name": "csv_part4", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                     "name": "csv_part5", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                      "name": "csv_part6", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                      "name": "csv_part7", 
-                                    "memory": "bank1"
+                                    "memory": "DDR[1]"
                                 },
                                 {
                                      "name": "buf_out", 
@@ -112,35 +113,35 @@
                                 },
                                 {
                                     "name": "csv_part0", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                     "name": "csv_part1", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                     "name": "csv_part2", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                     "name": "csv_part3", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                     "name": "csv_part4", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                     "name": "csv_part5", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                      "name": "csv_part6", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                      "name": "csv_part7", 
-                                    "memory": "bank2"
+                                    "memory": "DDR[2]"
                                 },
                                 {
                                      "name": "buf_out", 

-Original file line number
+Diff line change
 ::
 +   _u25_
    u50
    zc
    vck
Original file line number	Diff line number	Diff line change
`@@ -10,6 +10,7 @@`
`10`	`10`	`"aws"`
`11`	`11`	`],`
`12`	`12`	`"platform_blacklist": [`
	`13`	`+ "_u25_",`
`13`	`14`	`"u50",`
`14`	`15`	`"zc",`
`15`	`16`	`"vck"`
`@@ -62,35 +63,35 @@`
`62`	`63`	`},`
`63`	`64`	`{`
`64`	`65`	`"name": "csv_part0",`
`65`		`- "memory": "bank1"`
	`66`	`+ "memory": "DDR[1]"`
`66`	`67`	`},`
`67`	`68`	`{`
`68`	`69`	`"name": "csv_part1",`
`69`		`- "memory": "bank1"`
	`70`	`+ "memory": "DDR[1]"`
`70`	`71`	`},`
`71`	`72`	`{`
`72`	`73`	`"name": "csv_part2",`
`73`		`- "memory": "bank1"`
	`74`	`+ "memory": "DDR[1]"`
`74`	`75`	`},`
`75`	`76`	`{`
`76`	`77`	`"name": "csv_part3",`
`77`		`- "memory": "bank1"`
	`78`	`+ "memory": "DDR[1]"`
`78`	`79`	`},`
`79`	`80`	`{`
`80`	`81`	`"name": "csv_part4",`
`81`		`- "memory": "bank1"`
	`82`	`+ "memory": "DDR[1]"`
`82`	`83`	`},`
`83`	`84`	`{`
`84`	`85`	`"name": "csv_part5",`
`85`		`- "memory": "bank1"`
	`86`	`+ "memory": "DDR[1]"`
`86`	`87`	`},`
`87`	`88`	`{`
`88`	`89`	`"name": "csv_part6",`
`89`		`- "memory": "bank1"`
	`90`	`+ "memory": "DDR[1]"`
`90`	`91`	`},`
`91`	`92`	`{`
`92`	`93`	`"name": "csv_part7",`
`93`		`- "memory": "bank1"`
	`94`	`+ "memory": "DDR[1]"`
`94`	`95`	`},`
`95`	`96`	`{`
`96`	`97`	`"name": "buf_out",`
`@@ -112,35 +113,35 @@`
`112`	`113`	`},`
`113`	`114`	`{`
`114`	`115`	`"name": "csv_part0",`
`115`		`- "memory": "bank2"`
	`116`	`+ "memory": "DDR[2]"`
`116`	`117`	`},`
`117`	`118`	`{`
`118`	`119`	`"name": "csv_part1",`
`119`		`- "memory": "bank2"`
	`120`	`+ "memory": "DDR[2]"`
`120`	`121`	`},`
`121`	`122`	`{`
`122`	`123`	`"name": "csv_part2",`
`123`		`- "memory": "bank2"`
	`124`	`+ "memory": "DDR[2]"`
`124`	`125`	`},`
`125`	`126`	`{`
`126`	`127`	`"name": "csv_part3",`
`127`		`- "memory": "bank2"`
	`128`	`+ "memory": "DDR[2]"`
`128`	`129`	`},`
`129`	`130`	`{`
`130`	`131`	`"name": "csv_part4",`
`131`		`- "memory": "bank2"`
	`132`	`+ "memory": "DDR[2]"`
`132`	`133`	`},`
`133`	`134`	`{`
`134`	`135`	`"name": "csv_part5",`
`135`		`- "memory": "bank2"`
	`136`	`+ "memory": "DDR[2]"`
`136`	`137`	`},`
`137`	`138`	`{`
`138`	`139`	`"name": "csv_part6",`
`139`		`- "memory": "bank2"`
	`140`	`+ "memory": "DDR[2]"`
`140`	`141`	`},`
`141`	`142`	`{`
`142`	`143`	`"name": "csv_part7",`
`143`		`- "memory": "bank2"`
	`144`	`+ "memory": "DDR[2]"`
`144`	`145`	`},`
`145`	`146`	`{`
`146`	`147`	`"name": "buf_out",`