[AIE2P] Add a base lit test with unallocated 2D/3D regs before main Greedy run

Co-Authored-By: Krishnam Tibrewala <[email protected]>

Author: andcarminati

llvm/test/CodeGen/AIE/aie2p/ra/staged-rewrite-unallocated.mir

@@ -0,0 +1,79 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+#
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
+
+# RUN: llc -O2 -mtriple=aie2p -verify-machineinstrs -start-before=greedy \
+# RUN: -stop-before=virtregrewriter %s -o - | FileCheck %s
+
+# This test exposes some rewriting opportunities. Please note
+# that the registers directly used by the 3d instruction should not touched
+# because they already have physical registers assigned (are allocated).
+
+---
+name:            rewrite_unallocated
+alignment:       16
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: rewrite_unallocated
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV_RLC_imm11_pseudo:%[0-9]+]]:erf2 = MOV_RLC_imm11_pseudo 0
+  ; CHECK-NEXT:   undef [[VBCST_32_:%[0-9]+]].sub_512_lo:vec1024 = VBCST_32 [[MOV_RLC_imm11_pseudo]]
+  ; CHECK-NEXT:   [[MOV_PD_imm11_pseudo:%[0-9]+]]:em_as_32bit = MOV_PD_imm11_pseudo 0
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:edjl = COPY [[MOV_PD_imm11_pseudo]]
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:ednl = COPY [[MOV_PD_imm11_pseudo]]
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:edcl = COPY [[MOV_PD_imm11_pseudo]]
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:ednh = COPY [[MOV_PD_imm11_pseudo]]
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:edch = COPY [[MOV_PD_imm11_pseudo]]
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:edjh = COPY [[COPY]]
+  ; CHECK-NEXT:   [[VBCST_32_:%[0-9]+]].sub_512_hi:vec1024 = COPY [[VBCST_32_]].sub_512_lo
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:eldfiforeg = COPY [[VBCST_32_]]
+  ; CHECK-NEXT:   [[MOV_PD_imm11_pseudo1:%[0-9]+]]:eps = MOV_PD_imm11_pseudo 0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:edcl = COPY [[COPY2]]
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:ednl = COPY [[COPY1]]
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:edjl = COPY [[COPY]]
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:em_as_32bit = COPY [[MOV_PD_imm11_pseudo]]
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:edch = COPY [[COPY4]]
+  ; CHECK-NEXT:   [[COPY12:%[0-9]+]]:ednh = COPY [[COPY3]]
+  ; CHECK-NEXT:   [[COPY13:%[0-9]+]]:edjh = COPY [[COPY5]]
+  ; CHECK-NEXT:   undef [[COPY14:%[0-9]+]].sub_ptr:epsrfldf = COPY [[MOV_PD_imm11_pseudo1]]
+  ; CHECK-NEXT:   [[COPY14:%[0-9]+]].sub_fifo:epsrfldf = COPY [[COPY6]]
+  ; CHECK-NEXT:   [[COPY14:%[0-9]+]].sub_avail:epsrfldf = COPY [[MOV_RLC_imm11_pseudo]]
+  ; CHECK-NEXT:   dead [[VLD_POP_576_3D_pseudo_split:%[0-9]+]]:vec576, dead [[COPY14:%[0-9]+]].sub_ptr:epsrfldf, dead [[COPY14:%[0-9]+]].sub_fifo:epsrfldf, dead [[COPY14:%[0-9]+]].sub_avail:epsrfldf, dead [[COPY7:%[0-9]+]]:edcl, dead [[COPY11:%[0-9]+]]:edch = VLD_POP_576_3D_pseudo_split [[COPY14]].sub_ptr, [[COPY14]].sub_fifo, [[COPY14]].sub_avail, [[COPY10]], [[COPY8]], [[COPY9]], [[COPY7]], undef %23:em_as_32bit, [[COPY12]], [[COPY13]], [[COPY11]], implicit-def $srfifo_uf :: (load unknown-size from `ptr addrspace(5) null`, align 1, addrspace 5)
+  ; CHECK-NEXT:   PseudoJ_jump_imm %bb.1
+  bb.0:
+    successors: %bb.1(0x80000000)
+
+    %9:erf2 = MOV_RLC_imm11_pseudo 0
+    undef %8.sub_512_lo:vec1024 = VBCST_32 %9
+    undef %14.sub_mod:eds = MOV_PD_imm11_pseudo 0
+    %14.sub_dim_stride:eds = COPY %14.sub_mod
+    %14.sub_dim_size:eds = COPY %14.sub_mod
+    %14.sub_dim_count:eds = COPY %14.sub_mod
+    %14.sub_hi_dim_then_sub_dim_size:eds = COPY %14.sub_mod
+    %14.sub_hi_dim_then_sub_dim_count:eds = COPY %14.sub_mod
+    %14.sub_hi_dim_then_sub_dim_stride:eds = COPY %14.sub_dim_stride
+    %8.sub_512_hi:vec1024 = COPY %8.sub_512_lo
+    %12:eldfiforeg = COPY %8
+    %7:eps = MOV_PD_imm11_pseudo 0
+
+  bb.1:
+    successors: %bb.1(0x80000000)
+
+    %23:eds = COPY %14
+    undef %22.sub_ptr:epsrfldf = COPY %7
+    %22.sub_fifo:epsrfldf = COPY %12
+    %22.sub_avail:epsrfldf = COPY %9
+    dead %13:vec576, dead %22.sub_ptr:epsrfldf, dead %22.sub_fifo:epsrfldf, dead %22.sub_avail:epsrfldf, dead %23.sub_dim_count:eds, dead %23.sub_hi_dim_then_sub_dim_count:eds = VLD_POP_576_3D_pseudo_split %22.sub_ptr, %22.sub_fifo, %22.sub_avail, %23.sub_mod, %23.sub_dim_size, %23.sub_dim_stride, %23.sub_dim_count, undef %23.sub_hi_dim_then_sub_mod, %23.sub_hi_dim_then_sub_dim_size, %23.sub_hi_dim_then_sub_dim_stride, %23.sub_hi_dim_then_sub_dim_count, implicit-def $srfifo_uf :: (load unknown-size from `ptr addrspace(5) null`, align 1, addrspace 5)
+    PseudoJ_jump_imm %bb.1
+
+...