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[AIE2] Tests for instrinsic lowering using shufflevector
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‎llvm/test/CodeGen/AIE/aie2/intrinsics-shufflevec.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;
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; This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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; See https://llvm.org/LICENSE.txt for license information.
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; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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;
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; (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
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; RUN: llc -O2 -mtriple=aie2 -verify-machineinstrs --issue-limit=1 %s -o - | FileCheck %s
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define <8 x i32> @test_extract_vector(<16 x i32> noundef %a, i32 noundef %idx) {
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; CHECK-LABEL: test_extract_vector:
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; CHECK: .p2align 4
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: nopb ; nopa ; nops ; jz r0, #.LBB0_2; nopv
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; CHECK-NEXT: nopx // Delay Slot 5
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; CHECK-NEXT: nop // Delay Slot 4
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; CHECK-NEXT: nop // Delay Slot 3
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; CHECK-NEXT: mov r8, r16 // Delay Slot 2
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; CHECK-NEXT: mov r9, r17 // Delay Slot 1
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; CHECK-NEXT: // %bb.1: // %if.end
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; CHECK-NEXT: mova r16, #8; nopb ; nopxm
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; CHECK-NEXT: vextract.s32 r0, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #9
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; CHECK-NEXT: vextract.s32 r1, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #10
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; CHECK-NEXT: vextract.s32 r2, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #11
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; CHECK-NEXT: vextract.s32 r3, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #12
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; CHECK-NEXT: vextract.s32 r4, x2, r16
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; CHECK-NEXT: j #.LBB0_3
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; CHECK-NEXT: nop // Delay Slot 5
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; CHECK-NEXT: mova r16, #13 // Delay Slot 4
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; CHECK-NEXT: vextract.s32 r5, x2, r16 // Delay Slot 3
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; CHECK-NEXT: movx r17, #15 // Delay Slot 2
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; CHECK-NEXT: mova r16, #14 // Delay Slot 1
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2: // %if.then
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; CHECK-NEXT: nopb ; mova r16, #0; nops ; nopxm ; nopv
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; CHECK-NEXT: nopa ; vextract.s32 r0, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #1
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; CHECK-NEXT: vextract.s32 r1, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #2
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; CHECK-NEXT: vextract.s32 r2, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #3
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; CHECK-NEXT: vextract.s32 r3, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #4
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; CHECK-NEXT: vextract.s32 r4, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #5
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; CHECK-NEXT: vextract.s32 r5, x2, r16
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; CHECK-NEXT: movx r17, #7
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; CHECK-NEXT: mova r16, #6
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_3: // %return
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; CHECK-NEXT: nopa ; nopb ; nopx ; vextract.s32 r6, x2, r17; nops
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; CHECK-NEXT: nop
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; CHECK-NEXT: mov r17, r9
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; CHECK-NEXT: vextract.s32 r7, x2, r16
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; CHECK-NEXT: vpush.lo.32 x0, r6, x0
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; CHECK-NEXT: vpush.lo.32 x0, r7, x0
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; CHECK-NEXT: vpush.lo.32 x0, r5, x0
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; CHECK-NEXT: vpush.lo.32 x0, r4, x0
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; CHECK-NEXT: ret lr
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; CHECK-NEXT: vpush.lo.32 x0, r3, x0 // Delay Slot 5
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; CHECK-NEXT: vpush.lo.32 x0, r2, x0 // Delay Slot 4
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; CHECK-NEXT: vpush.lo.32 x0, r1, x0 // Delay Slot 3
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0 // Delay Slot 2
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; CHECK-NEXT: mov r16, r8 // Delay Slot 1
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entry:
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%cmp = icmp eq i32 %idx, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%shuffle = shufflevector <16 x i32> %a, <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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br label %return
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if.end:
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%shuffle1 = shufflevector <16 x i32> %a, <16 x i32> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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br label %return
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return:
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%retval.0 = phi <8 x i32> [ %shuffle, %if.then ], [ %shuffle1, %if.end ]
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ret <8 x i32> %retval.0
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}
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define <16 x i32> @test_insert_vector(<16 x i32> noundef %a, i32 noundef %idx, <8 x i32> noundef %b) {
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; CHECK-LABEL: test_insert_vector:
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; CHECK: .p2align 4
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: nopa ; nopb ; nopx ; mov r25, r17
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; CHECK-NEXT: mov r26, r18
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; CHECK-NEXT: mov r27, r19
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; CHECK-NEXT: mova r18, #1
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; CHECK-NEXT: mova r19, #2
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; CHECK-NEXT: mova r17, #3
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; CHECK-NEXT: mov r24, r16
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; CHECK-NEXT: mova r16, #0
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; CHECK-NEXT: vextract.s32 r1, x4, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #4
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; CHECK-NEXT: vextract.s32 r2, x4, r18
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; CHECK-NEXT: vextract.s32 r3, x4, r19
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; CHECK-NEXT: vextract.s32 r4, x4, r17
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; CHECK-NEXT: vextract.s32 r5, x4, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #5
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; CHECK-NEXT: vextract.s32 r6, x4, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #6
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; CHECK-NEXT: vextract.s32 r7, x4, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #7
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: vextract.s32 r8, x4, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: vpush.lo.32 x0, r8, x0
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; CHECK-NEXT: vpush.lo.32 x0, r7, x0
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; CHECK-NEXT: vpush.lo.32 x0, r6, x0
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; CHECK-NEXT: vpush.lo.32 x0, r5, x0
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; CHECK-NEXT: jz r0, #.LBB1_2
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; CHECK-NEXT: vpush.lo.32 x0, r4, x0 // Delay Slot 5
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; CHECK-NEXT: vpush.lo.32 x0, r3, x0 // Delay Slot 4
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; CHECK-NEXT: vpush.lo.32 x0, r2, x0 // Delay Slot 3
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; CHECK-NEXT: vpush.lo.32 x0, r1, x0 // Delay Slot 2
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; CHECK-NEXT: nop // Delay Slot 1
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; CHECK-NEXT: // %bb.1: // %if.end
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; CHECK-NEXT: mova r16, #3
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; CHECK-NEXT: mova r17, #0
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; CHECK-NEXT: vextract.s32 r1, x2, r18
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; CHECK-NEXT: vextract.s32 r2, x2, r19
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; CHECK-NEXT: movx r18, #4
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; CHECK-NEXT: mova r19, #5
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; CHECK-NEXT: vextract.s32 r3, x2, r16
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; CHECK-NEXT: vextract.s32 r0, x2, r17
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; CHECK-NEXT: vextract.s32 r8, x0, r17
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; CHECK-NEXT: movx r16, #6
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; CHECK-NEXT: mova r17, #1
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; CHECK-NEXT: vextract.s32 r4, x2, r18
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; CHECK-NEXT: vextract.s32 r5, x2, r19
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; CHECK-NEXT: vextract.s32 r12, x0, r18
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; CHECK-NEXT: vextract.s32 r13, x0, r19
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; CHECK-NEXT: vextract.s32 r6, x2, r16
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; CHECK-NEXT: vextract.s32 r9, x0, r17
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; CHECK-NEXT: movx r16, #7
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; CHECK-NEXT: mova r17, #2
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; CHECK-NEXT: vextract.s32 r10, x0, r17
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; CHECK-NEXT: vextract.s32 r7, x2, r16
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; CHECK-NEXT: vextract.s32 r14, x0, r16
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; CHECK-NEXT: j #.LBB1_3
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; CHECK-NEXT: mova r17, #3 // Delay Slot 5
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; CHECK-NEXT: mova r16, #6 // Delay Slot 4
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; CHECK-NEXT: vextract.s32 r11, x0, r17 // Delay Slot 3
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; CHECK-NEXT: vextract.s32 r15, x0, r16 // Delay Slot 2
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; CHECK-NEXT: nop // Delay Slot 1
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB1_2: // %if.then
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; CHECK-NEXT: nopa ; nopb ; nopx ; vextract.s32 r3, x0, r17; nops
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; CHECK-NEXT: vextract.s32 r11, x2, r17
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; CHECK-NEXT: movx r16, #0
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; CHECK-NEXT: mova r17, #4
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; CHECK-NEXT: vextract.s32 r1, x0, r18
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; CHECK-NEXT: vextract.s32 r2, x0, r19
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; CHECK-NEXT: vextract.s32 r9, x2, r18
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; CHECK-NEXT: vextract.s32 r10, x2, r19
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; CHECK-NEXT: vextract.s32 r12, x2, r17
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; CHECK-NEXT: vextract.s32 r0, x0, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #4
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; CHECK-NEXT: vextract.s32 r4, x0, r16
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; CHECK-NEXT: movx r17, #5
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; CHECK-NEXT: mova r16, #5
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; CHECK-NEXT: vextract.s32 r13, x2, r17
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; CHECK-NEXT: vextract.s32 r5, x0, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #6
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; CHECK-NEXT: vextract.s32 r6, x0, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #7
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; CHECK-NEXT: vextract.s32 r7, x0, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #0
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; CHECK-NEXT: vextract.s32 r8, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #7
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; CHECK-NEXT: vextract.s32 r14, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #6
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; CHECK-NEXT: vextract.s32 r15, x2, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB1_3: // %cleanup
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; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; mov r19, r27; nopv
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; CHECK-NEXT: mov r18, r26
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; CHECK-NEXT: mov r17, r25
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; CHECK-NEXT: vpush.lo.32 x0, r14, x0
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; CHECK-NEXT: vpush.lo.32 x0, r15, x0
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; CHECK-NEXT: vpush.lo.32 x0, r13, x0
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; CHECK-NEXT: vpush.lo.32 x0, r12, x0
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; CHECK-NEXT: vpush.lo.32 x0, r11, x0
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; CHECK-NEXT: vpush.lo.32 x0, r10, x0
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; CHECK-NEXT: vpush.lo.32 x0, r9, x0
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; CHECK-NEXT: vpush.lo.32 x0, r8, x0
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; CHECK-NEXT: vpush.lo.32 x0, r7, x0
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; CHECK-NEXT: vpush.lo.32 x0, r6, x0
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; CHECK-NEXT: vpush.lo.32 x0, r5, x0
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; CHECK-NEXT: vpush.lo.32 x0, r4, x0
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; CHECK-NEXT: ret lr
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; CHECK-NEXT: vpush.lo.32 x0, r3, x0 // Delay Slot 5
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; CHECK-NEXT: vpush.lo.32 x0, r2, x0 // Delay Slot 4
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; CHECK-NEXT: vpush.lo.32 x0, r1, x0 // Delay Slot 3
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0 // Delay Slot 2
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; CHECK-NEXT: mov r16, r24 // Delay Slot 1
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entry:
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%shuffle = shufflevector <8 x i32> %b, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%cmp = icmp eq i32 %idx, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%shuffle1 = shufflevector <16 x i32> %shuffle, <16 x i32> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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br label %cleanup
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if.end: ;
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%shuffle2 = shufflevector <16 x i32> %a, <16 x i32> %shuffle, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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br label %cleanup
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cleanup:
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%retval.0 = phi <16 x i32> [ %shuffle1, %if.then ], [ %shuffle2, %if.end ]
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ret <16 x i32> %retval.0
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}
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define <16 x i32> @test_concat_vector(<8 x i32> noundef %a, <8 x i32> noundef %b) {
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; CHECK-LABEL: test_concat_vector:
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; CHECK: .p2align 4
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: nopa ; nopx ; mov r24, r16
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; CHECK-NEXT: mova r16, #0
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; CHECK-NEXT: vextract.s32 r0, x2, r16
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; CHECK-NEXT: vextract.s32 r1, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #1
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; CHECK-NEXT: vextract.s32 r2, x2, r16
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; CHECK-NEXT: vextract.s32 r3, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #2
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; CHECK-NEXT: vextract.s32 r4, x2, r16
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; CHECK-NEXT: vextract.s32 r5, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #3
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; CHECK-NEXT: vextract.s32 r6, x2, r16
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; CHECK-NEXT: vextract.s32 r7, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #4
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; CHECK-NEXT: vextract.s32 r8, x2, r16
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; CHECK-NEXT: vextract.s32 r9, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #5
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; CHECK-NEXT: vextract.s32 r10, x2, r16
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; CHECK-NEXT: vextract.s32 r11, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #7
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; CHECK-NEXT: vextract.s32 r12, x2, r16
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; CHECK-NEXT: vextract.s32 r13, x4, r16
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; CHECK-NEXT: nop
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; CHECK-NEXT: mova r16, #6
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; CHECK-NEXT: vextract.s32 r14, x2, r16
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; CHECK-NEXT: vextract.s32 r15, x4, r16
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; CHECK-NEXT: vpush.lo.32 x0, r13, x0
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; CHECK-NEXT: vpush.lo.32 x0, r15, x0
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; CHECK-NEXT: vpush.lo.32 x0, r11, x0
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; CHECK-NEXT: vpush.lo.32 x0, r9, x0
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; CHECK-NEXT: vpush.lo.32 x0, r7, x0
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; CHECK-NEXT: vpush.lo.32 x0, r5, x0
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; CHECK-NEXT: vpush.lo.32 x0, r3, x0
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; CHECK-NEXT: vpush.lo.32 x0, r1, x0
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; CHECK-NEXT: vpush.lo.32 x0, r12, x0
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; CHECK-NEXT: vpush.lo.32 x0, r14, x0
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; CHECK-NEXT: vpush.lo.32 x0, r10, x0
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; CHECK-NEXT: vpush.lo.32 x0, r8, x0
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; CHECK-NEXT: ret lr
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; CHECK-NEXT: vpush.lo.32 x0, r6, x0 // Delay Slot 5
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; CHECK-NEXT: vpush.lo.32 x0, r4, x0 // Delay Slot 4
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; CHECK-NEXT: vpush.lo.32 x0, r2, x0 // Delay Slot 3
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0 // Delay Slot 2
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; CHECK-NEXT: mov r16, r24 // Delay Slot 1
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entry:
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%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i32> %shuffle
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}
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define <16 x i32> @test_set_vector(i32 noundef %idx, <8 x i32> noundef %a) {
302+
; CHECK-LABEL: test_set_vector:
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; CHECK: .p2align 4
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; CHECK-NEXT: // %bb.0: // %entry
305+
; CHECK-NEXT: nopa ; nopb ; nopx ; mov r9, r16
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; CHECK-NEXT: mova r16, #0
307+
; CHECK-NEXT: vextract.s32 r1, x2, r16
308+
; CHECK-NEXT: eqz r0, r0
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; CHECK-NEXT: mova r16, #1
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; CHECK-NEXT: vextract.s32 r2, x2, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #2
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; CHECK-NEXT: vextract.s32 r3, x2, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #3
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; CHECK-NEXT: vextract.s32 r4, x2, r16
317+
; CHECK-NEXT: vpush.lo.32 x0, r0, x0
318+
; CHECK-NEXT: mova r16, #4
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; CHECK-NEXT: vextract.s32 r5, x2, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #5
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; CHECK-NEXT: vextract.s32 r6, x2, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: mova r16, #6
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; CHECK-NEXT: vextract.s32 r7, x2, r16
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; CHECK-NEXT: vpush.lo.32 x0, r0, x0
327+
; CHECK-NEXT: mova r16, #7
328+
; CHECK-NEXT: vpush.lo.32 x0, r0, x0
329+
; CHECK-NEXT: vextract.s32 r8, x2, r16
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; CHECK-NEXT: add r16, r0, #-1
331+
; CHECK-NEXT: vpush.lo.32 x0, r0, x0
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; CHECK-NEXT: vpush.lo.32 x0, r8, x0
333+
; CHECK-NEXT: vpush.lo.32 x0, r7, x0
334+
; CHECK-NEXT: vpush.lo.32 x0, r6, x0
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; CHECK-NEXT: vpush.lo.32 x0, r5, x0
336+
; CHECK-NEXT: vpush.lo.32 x0, r4, x0
337+
; CHECK-NEXT: vpush.lo.32 x0, r3, x0
338+
; CHECK-NEXT: vpush.lo.32 x0, r2, x0
339+
; CHECK-NEXT: vpush.lo.32 x0, r1, x0
340+
; CHECK-NEXT: vpush.lo.32 x2, r8, x0
341+
; CHECK-NEXT: vpush.lo.32 x2, r7, x2
342+
; CHECK-NEXT: vpush.lo.32 x2, r6, x2
343+
; CHECK-NEXT: vpush.lo.32 x2, r5, x2
344+
; CHECK-NEXT: vpush.lo.32 x2, r4, x2
345+
; CHECK-NEXT: vpush.lo.32 x2, r3, x2
346+
; CHECK-NEXT: vpush.lo.32 x2, r2, x2
347+
; CHECK-NEXT: vpush.lo.32 x2, r1, x2
348+
; CHECK-NEXT: vpush.lo.32 x2, r0, x2
349+
; CHECK-NEXT: vpush.lo.32 x2, r0, x2
350+
; CHECK-NEXT: vpush.lo.32 x2, r0, x2
351+
; CHECK-NEXT: vpush.lo.32 x2, r0, x2
352+
; CHECK-NEXT: vpush.lo.32 x2, r0, x2
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; CHECK-NEXT: ret lr
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; CHECK-NEXT: vpush.lo.32 x2, r0, x2 // Delay Slot 5
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; CHECK-NEXT: vpush.lo.32 x2, r0, x2 // Delay Slot 4
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; CHECK-NEXT: vpush.lo.32 x2, r0, x2 // Delay Slot 3
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; CHECK-NEXT: vsel.32 x0, x0, x2, r16 // Delay Slot 2
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; CHECK-NEXT: mov r16, r9 // Delay Slot 1
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entry:
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%cmp = icmp eq i32 %idx, 0
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%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%shuffle1 = shufflevector <8 x i32> %a, <8 x i32> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%retval.0 = select i1 %cmp, <16 x i32> %shuffle, <16 x i32> %shuffle1
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ret <16 x i32> %retval.0
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}
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define i32 @test_extract_elem(<8 x i32> noundef %a, i32 noundef %idx) {
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; CHECK-LABEL: test_extract_elem:
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; CHECK: .p2align 4
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; CHECK-NEXT: // %bb.0: // %entry
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; CHECK-NEXT: nopa ; nopb ; ret lr ; nopm ; nops
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; CHECK-NEXT: mov r2, r16 // Delay Slot 5
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; CHECK-NEXT: mov r16, r1 // Delay Slot 4
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; CHECK-NEXT: vextract.s32 r0, x0, r16 // Delay Slot 3
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; CHECK-NEXT: nop // Delay Slot 2
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; CHECK-NEXT: mov r16, r2 // Delay Slot 1
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entry:
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%vecext = extractelement <8 x i32> %a, i32 %idx
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ret i32 %vecext
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}

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