@@ -86,11 +86,48 @@ AIE2PreLegalizerCombinerImpl::AIE2PreLegalizerCombinerImpl(
8686{
8787}
8888
89+ std::function<std::optional<int32_t >()>
90+ sectionGenerator (const int32_t From, const int32_t To,
91+ const int32_t Partitions) {
92+ int32_t RoundSize = To / Partitions;
93+ int32_t Index = From;
94+ return [RoundSize, Index, Partitions, To]() mutable {
95+ int32_t Next = (Index / Partitions) + RoundSize * (Index % Partitions) +
96+ (Index % Partitions);
97+ std::optional<int32_t > Return = std::optional<int32_t >(Next);
98+ if (Index++ == To)
99+ Return = {};
100+ return Return;
101+ };
102+ }
103+
89104bool AIE2PreLegalizerCombinerImpl::tryCombineShuffleVector (
90105 MachineInstr &MI) const {
106+ const Register DstReg = MI.getOperand (0 ).getReg ();
107+ const LLT DstTy = MRI.getType (DstReg);
108+ const LLT SrcTy = MRI.getType (MI.getOperand (1 ).getReg ());
109+ const unsigned DstNumElts = DstTy.isVector () ? DstTy.getNumElements () : 1 ;
110+ const unsigned SrcNumElts = SrcTy.isVector () ? SrcTy.getNumElements () : 1 ;
111+ MachineIRBuilder MIB (MI);
112+ MachineRegisterInfo &MRI = *MIB.getMRI ();
113+
91114 if (Helper.tryCombineShuffleVector (MI))
92115 return true ;
93116
117+ std::function<std::optional<int32_t >()> FourPartitions =
118+ sectionGenerator (0 , DstNumElts - 1 , 4 );
119+ if (Helper.matchCombineShuffleVectorSimple (MI, FourPartitions, DstNumElts)) {
120+ const Register Src1 = MI.getOperand (1 ).getReg ();
121+ const Register Src2 = MI.getOperand (2 ).getReg ();
122+ const Register ShuffleModeReg =
123+ MRI.createGenericVirtualRegister (LLT::scalar (32 ));
124+
125+ MIB.buildConstant (ShuffleModeReg, 29 );
126+ MIB.buildInstr (AIE2::G_AIE_VSHUFFLE, {DstReg},
127+ {Src1, Src2, ShuffleModeReg});
128+ MI.eraseFromParent ();
129+ return true ;
130+ }
94131 return false ;
95132}
96133bool AIE2PreLegalizerCombinerImpl::tryCombineAll (MachineInstr &MI) const {
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