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[AIE2] Helper function for creating VSHUFFLE instructions
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2 files changed

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llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp

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@@ -152,6 +152,39 @@ bool AIE2PreLegalizerCombinerImpl::tryToCombineIntrinsic(
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return false;
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}
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bool createVShuffle(MachineInstr &MI, const LLT TargetTy, const uint8_t Mode) {
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MachineIRBuilder MIB(MI);
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MachineRegisterInfo &MRI = *MIB.getMRI();
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const Register DstReg = MI.getOperand(0).getReg();
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const LLT DstTy = MRI.getType(DstReg);
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if (DstTy != TargetTy)
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return false;
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const Register Src1 = MI.getOperand(1).getReg();
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const Register Src2 = MI.getOperand(2).getReg();
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const Register ShuffleModeReg =
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MRI.createGenericVirtualRegister(LLT::scalar(32));
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// This combiner only cares about the lower bits, so we can pad the
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// vector to cover the case where two separate vectors are shuffled.
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// together
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MIB.buildConstant(ShuffleModeReg, Mode);
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if (MRI.getType(Src1) == TargetTy) {
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MIB.buildInstr(AIE2::G_AIE_VSHUFFLE, {DstReg},
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{Src1, Src2, ShuffleModeReg});
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} else {
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// We reuse the same register since we ignore the high part of the vector
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const Register TmpRegister = MRI.createGenericVirtualRegister(TargetTy);
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MIB.buildConcatVectors(TmpRegister, {Src1, Src2});
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MIB.buildInstr(AIE2::G_AIE_VSHUFFLE, {DstReg},
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{TmpRegister, TmpRegister, ShuffleModeReg});
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}
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MI.eraseFromParent();
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return true;
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}
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CombinerHelper::GeneratorType sectionGenerator(const int32_t From,
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const int32_t To,
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const int32_t Partitions,

llvm/lib/Target/AIE/AIEInstrGISel.td

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@@ -96,6 +96,12 @@ def G_AIE_BROADCAST_VECTOR : AIEGenericInstruction {
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let hasSideEffects = false;
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}
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def G_AIE_VSHUFFLE : AIEGenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type0:$src2, type1:$mode);
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let hasSideEffects = false;
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}
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// Create a larger vector by padding undefined values in the high bits
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def G_AIE_PAD_VECTOR_UNDEF : AIEGenericInstruction {
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let OutOperandList = (outs type0:$dst);

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