@@ -152,6 +152,39 @@ bool AIE2PreLegalizerCombinerImpl::tryToCombineIntrinsic(
152152 return false ;
153153}
154154
155+ bool createVShuffle (MachineInstr &MI, const LLT TargetTy, const uint8_t Mode) {
156+ MachineIRBuilder MIB (MI);
157+ MachineRegisterInfo &MRI = *MIB.getMRI ();
158+ const Register DstReg = MI.getOperand (0 ).getReg ();
159+ const LLT DstTy = MRI.getType (DstReg);
160+
161+ if (DstTy != TargetTy)
162+ return false ;
163+
164+ const Register Src1 = MI.getOperand (1 ).getReg ();
165+ const Register Src2 = MI.getOperand (2 ).getReg ();
166+ const Register ShuffleModeReg =
167+ MRI.createGenericVirtualRegister (LLT::scalar (32 ));
168+
169+ // This combiner only cares about the lower bits, so we can pad the
170+ // vector to cover the case where two separate vectors are shuffled.
171+ // together
172+ MIB.buildConstant (ShuffleModeReg, Mode);
173+ if (MRI.getType (Src1) == TargetTy) {
174+ MIB.buildInstr (AIE2::G_AIE_VSHUFFLE, {DstReg},
175+ {Src1, Src2, ShuffleModeReg});
176+ } else {
177+ // We reuse the same register since we ignore the high part of the vector
178+ const Register TmpRegister = MRI.createGenericVirtualRegister (TargetTy);
179+ MIB.buildConcatVectors (TmpRegister, {Src1, Src2});
180+ MIB.buildInstr (AIE2::G_AIE_VSHUFFLE, {DstReg},
181+ {TmpRegister, TmpRegister, ShuffleModeReg});
182+ }
183+
184+ MI.eraseFromParent ();
185+ return true ;
186+ }
187+
155188CombinerHelper::GeneratorType sectionGenerator (const int32_t From,
156189 const int32_t To,
157190 const int32_t Partitions,
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