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ValentijnvdBeekValentijnvdBeek
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[GISel][CombinerHelper] Add two patterns that extract the first two chunks of a vector
1 parent 9c0f927 commit 50981ad

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6 files changed

+246
-156
lines changed

6 files changed

+246
-156
lines changed

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -408,6 +408,30 @@ bool CombinerHelper::tryCombineShuffleVector(MachineInstr &MI) {
408408
return true;
409409
}
410410

411+
// {1, 2, ..., |DstVector|} -> G_UNMERGE_VALUES
412+
// Extracts the first chunk of the same size of the destination vector from
413+
// the source
414+
GeneratorType FirstQuarter = adderGenerator(0, DstNumElts - 1, 1);
415+
if (matchCombineShuffleVector(MI, FirstQuarter, DstNumElts - 1)) {
416+
if (SrcTy == DstTy || ((SrcNumElts / 2) % 2) != 0 || SrcNumElts % DstNumElts != 0 )
417+
return false;
418+
createUnmergeValue(MI, MI.getOperand(1).getReg(), DstReg, 0);
419+
MI.eraseFromParent();
420+
return true;
421+
}
422+
423+
// {|DstVector|, |DstVector|+1, ..., 2 * |DstVector|} -> G_UNMERGE_VALUES
424+
// Extracts the second chunk of the same size of the destination vector from
425+
// the source
426+
GeneratorType SecondQuarter =
427+
adderGenerator(DstNumElts, (DstNumElts * 2) - 1, 1);
428+
if (matchCombineShuffleVector(MI, SecondQuarter, DstNumElts - 1)) {
429+
if (((SrcNumElts / 2) % 2) != 0 || SrcNumElts % DstNumElts != 0)
430+
return false;
431+
createUnmergeValue(MI, MI.getOperand(1).getReg(), DstReg, 1);
432+
MI.eraseFromParent();
433+
return true;
434+
}
411435
return false;
412436
}
413437

‎llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -216,16 +216,16 @@ body: |
216216
; CHECK-LABEL: name: shufflevector_not_all_ops_undef
217217
; CHECK: liveins: $d0
218218
; CHECK-NEXT: {{ $}}
219-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
220-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
221-
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<2 x s32>), [[COPY]], shufflemask(0, 1)
222-
; CHECK-NEXT: $d0 = COPY [[SHUF]](<2 x s32>)
223-
; CHECK-NEXT: RET_ReallyLR implicit $d0
224-
%1:_(<2 x s32>) = G_IMPLICIT_DEF
225-
%2:_(<2 x s32>) = COPY $d0
226-
%0:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2(<2 x s32>), shufflemask(0, 1)
227-
$d0 = COPY %0(<2 x s32>)
228-
RET_ReallyLR implicit $d0
219+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
220+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
221+
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[DEF]](<4 x s32>), [[COPY]], shufflemask(0, 1, 2, 1)
222+
; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>)
223+
; CHECK-NEXT: RET_ReallyLR implicit $q0
224+
%1:_(<4 x s32>) = G_IMPLICIT_DEF
225+
%2:_(<4 x s32>) = COPY $q0
226+
%0:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2(<4 x s32>), shufflemask(0, 1, 2, 1)
227+
$q0 = COPY %0(<4 x s32>)
228+
RET_ReallyLR implicit $q0
229229
230230
...
231231
---

‎llvm/test/CodeGen/AArch64/ext-narrow-index.ll‎

Lines changed: 40 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,7 @@ define <8 x i8> @i8_off8(<16 x i8> %arg1, <16 x i8> %arg2) {
4242
;
4343
; CHECK-GISEL-LABEL: i8_off8:
4444
; CHECK-GISEL: // %bb.0: // %entry
45-
; CHECK-GISEL-NEXT: ext v0.16b, v0.16b, v1.16b, #8
46-
; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
45+
; CHECK-GISEL-NEXT: mov d0, v0.d[1]
4746
; CHECK-GISEL-NEXT: ret
4847
entry:
4948
%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -118,11 +117,16 @@ entry:
118117
}
119118

120119
define <4 x i16> @i16_off8(<8 x i16> %arg1, <8 x i16> %arg2) {
121-
; CHECK-LABEL: i16_off8:
122-
; CHECK: // %bb.0: // %entry
123-
; CHECK-NEXT: mov v0.16b, v1.16b
124-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
125-
; CHECK-NEXT: ret
120+
; CHECK-SD-LABEL: i16_off8:
121+
; CHECK-SD: // %bb.0: // %entry
122+
; CHECK-SD-NEXT: mov v0.16b, v1.16b
123+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
124+
; CHECK-SD-NEXT: ret
125+
;
126+
; CHECK-GISEL-LABEL: i16_off8:
127+
; CHECK-GISEL: // %bb.0: // %entry
128+
; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
129+
; CHECK-GISEL-NEXT: ret
126130
entry:
127131
%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> %arg2, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
128132
ret <4 x i16> %shuffle
@@ -168,11 +172,16 @@ entry:
168172
}
169173

170174
define <2 x i32> @i32_off4(<4 x i32> %arg1, <4 x i32> %arg2) {
171-
; CHECK-LABEL: i32_off4:
172-
; CHECK: // %bb.0: // %entry
173-
; CHECK-NEXT: mov v0.16b, v1.16b
174-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
175-
; CHECK-NEXT: ret
175+
; CHECK-SD-LABEL: i32_off4:
176+
; CHECK-SD: // %bb.0: // %entry
177+
; CHECK-SD-NEXT: mov v0.16b, v1.16b
178+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
179+
; CHECK-SD-NEXT: ret
180+
;
181+
; CHECK-GISEL-LABEL: i32_off4:
182+
; CHECK-GISEL: // %bb.0: // %entry
183+
; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
184+
; CHECK-GISEL-NEXT: ret
176185
entry:
177186
%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> %arg2, <2 x i32> <i32 4, i32 5>
178187
ret <2 x i32> %shuffle
@@ -254,9 +263,7 @@ define <8 x i8> @i8_zero_off8(<16 x i8> %arg1) {
254263
;
255264
; CHECK-GISEL-LABEL: i8_zero_off8:
256265
; CHECK-GISEL: // %bb.0: // %entry
257-
; CHECK-GISEL-NEXT: movi v1.2d, #0000000000000000
258-
; CHECK-GISEL-NEXT: ext v0.16b, v0.16b, v1.16b, #8
259-
; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
266+
; CHECK-GISEL-NEXT: mov d0, v0.d[1]
260267
; CHECK-GISEL-NEXT: ret
261268
entry:
262269
%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -334,10 +341,15 @@ entry:
334341
}
335342

336343
define <4 x i16> @i16_zero_off8(<8 x i16> %arg1) {
337-
; CHECK-LABEL: i16_zero_off8:
338-
; CHECK: // %bb.0: // %entry
339-
; CHECK-NEXT: movi v0.2d, #0000000000000000
340-
; CHECK-NEXT: ret
344+
; CHECK-SD-LABEL: i16_zero_off8:
345+
; CHECK-SD: // %bb.0: // %entry
346+
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
347+
; CHECK-SD-NEXT: ret
348+
;
349+
; CHECK-GISEL-LABEL: i16_zero_off8:
350+
; CHECK-GISEL: // %bb.0: // %entry
351+
; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
352+
; CHECK-GISEL-NEXT: ret
341353
entry:
342354
%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
343355
ret <4 x i16> %shuffle
@@ -385,10 +397,15 @@ entry:
385397
}
386398

387399
define <2 x i32> @i32_zero_off4(<4 x i32> %arg1) {
388-
; CHECK-LABEL: i32_zero_off4:
389-
; CHECK: // %bb.0: // %entry
390-
; CHECK-NEXT: movi v0.2d, #0000000000000000
391-
; CHECK-NEXT: ret
400+
; CHECK-SD-LABEL: i32_zero_off4:
401+
; CHECK-SD: // %bb.0: // %entry
402+
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
403+
; CHECK-SD-NEXT: ret
404+
;
405+
; CHECK-GISEL-LABEL: i32_zero_off4:
406+
; CHECK-GISEL: // %bb.0: // %entry
407+
; CHECK-GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
408+
; CHECK-GISEL-NEXT: ret
392409
entry:
393410
%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> <i32 4, i32 5>
394411
ret <2 x i32> %shuffle

‎llvm/test/CodeGen/AArch64/vecreduce-add.ll‎

Lines changed: 10 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -6305,69 +6305,16 @@ entry:
63056305
}
63066306

63076307
define i32 @add_pair_v8i16_v4i32_double_sext_zext_shuffle(<8 x i16> %ax, <8 x i16> %ay, <8 x i16> %bx, <8 x i16> %by) {
6308-
; CHECK-SD-BASE-LABEL: add_pair_v8i16_v4i32_double_sext_zext_shuffle:
6309-
; CHECK-SD-BASE: // %bb.0: // %entry
6310-
; CHECK-SD-BASE-NEXT: uaddlp v1.4s, v1.8h
6311-
; CHECK-SD-BASE-NEXT: uaddlp v3.4s, v3.8h
6312-
; CHECK-SD-BASE-NEXT: uadalp v1.4s, v0.8h
6313-
; CHECK-SD-BASE-NEXT: uadalp v3.4s, v2.8h
6314-
; CHECK-SD-BASE-NEXT: add v0.4s, v3.4s, v1.4s
6315-
; CHECK-SD-BASE-NEXT: addv s0, v0.4s
6316-
; CHECK-SD-BASE-NEXT: fmov w0, s0
6317-
; CHECK-SD-BASE-NEXT: ret
6318-
;
6319-
; CHECK-SD-DOT-LABEL: add_pair_v8i16_v4i32_double_sext_zext_shuffle:
6320-
; CHECK-SD-DOT: // %bb.0: // %entry
6321-
; CHECK-SD-DOT-NEXT: uaddlp v1.4s, v1.8h
6322-
; CHECK-SD-DOT-NEXT: uaddlp v3.4s, v3.8h
6323-
; CHECK-SD-DOT-NEXT: uadalp v1.4s, v0.8h
6324-
; CHECK-SD-DOT-NEXT: uadalp v3.4s, v2.8h
6325-
; CHECK-SD-DOT-NEXT: add v0.4s, v3.4s, v1.4s
6326-
; CHECK-SD-DOT-NEXT: addv s0, v0.4s
6327-
; CHECK-SD-DOT-NEXT: fmov w0, s0
6328-
; CHECK-SD-DOT-NEXT: ret
6329-
;
6330-
; CHECK-GI-BASE-LABEL: add_pair_v8i16_v4i32_double_sext_zext_shuffle:
6331-
; CHECK-GI-BASE: // %bb.0: // %entry
6332-
; CHECK-GI-BASE-NEXT: ushll v4.4s, v0.4h, #0
6333-
; CHECK-GI-BASE-NEXT: ushll2 v0.4s, v0.8h, #0
6334-
; CHECK-GI-BASE-NEXT: ushll v5.4s, v1.4h, #0
6335-
; CHECK-GI-BASE-NEXT: ushll2 v1.4s, v1.8h, #0
6336-
; CHECK-GI-BASE-NEXT: ushll v6.4s, v2.4h, #0
6337-
; CHECK-GI-BASE-NEXT: ushll2 v2.4s, v2.8h, #0
6338-
; CHECK-GI-BASE-NEXT: ushll v7.4s, v3.4h, #0
6339-
; CHECK-GI-BASE-NEXT: ushll2 v3.4s, v3.8h, #0
6340-
; CHECK-GI-BASE-NEXT: add v0.4s, v4.4s, v0.4s
6341-
; CHECK-GI-BASE-NEXT: add v1.4s, v5.4s, v1.4s
6342-
; CHECK-GI-BASE-NEXT: add v2.4s, v6.4s, v2.4s
6343-
; CHECK-GI-BASE-NEXT: add v3.4s, v7.4s, v3.4s
6344-
; CHECK-GI-BASE-NEXT: add v0.4s, v0.4s, v1.4s
6345-
; CHECK-GI-BASE-NEXT: add v1.4s, v2.4s, v3.4s
6346-
; CHECK-GI-BASE-NEXT: add v0.4s, v0.4s, v1.4s
6347-
; CHECK-GI-BASE-NEXT: addv s0, v0.4s
6348-
; CHECK-GI-BASE-NEXT: fmov w0, s0
6349-
; CHECK-GI-BASE-NEXT: ret
6350-
;
6351-
; CHECK-GI-DOT-LABEL: add_pair_v8i16_v4i32_double_sext_zext_shuffle:
6352-
; CHECK-GI-DOT: // %bb.0: // %entry
6353-
; CHECK-GI-DOT-NEXT: ushll v4.4s, v0.4h, #0
6354-
; CHECK-GI-DOT-NEXT: ushll2 v0.4s, v0.8h, #0
6355-
; CHECK-GI-DOT-NEXT: ushll v5.4s, v1.4h, #0
6356-
; CHECK-GI-DOT-NEXT: ushll2 v1.4s, v1.8h, #0
6357-
; CHECK-GI-DOT-NEXT: ushll v6.4s, v2.4h, #0
6358-
; CHECK-GI-DOT-NEXT: ushll2 v2.4s, v2.8h, #0
6359-
; CHECK-GI-DOT-NEXT: ushll v7.4s, v3.4h, #0
6360-
; CHECK-GI-DOT-NEXT: ushll2 v3.4s, v3.8h, #0
6361-
; CHECK-GI-DOT-NEXT: add v0.4s, v4.4s, v0.4s
6362-
; CHECK-GI-DOT-NEXT: add v1.4s, v5.4s, v1.4s
6363-
; CHECK-GI-DOT-NEXT: add v2.4s, v6.4s, v2.4s
6364-
; CHECK-GI-DOT-NEXT: add v3.4s, v7.4s, v3.4s
6365-
; CHECK-GI-DOT-NEXT: add v0.4s, v0.4s, v1.4s
6366-
; CHECK-GI-DOT-NEXT: add v1.4s, v2.4s, v3.4s
6367-
; CHECK-GI-DOT-NEXT: add v0.4s, v0.4s, v1.4s
6368-
; CHECK-GI-DOT-NEXT: addv s0, v0.4s
6369-
; CHECK-GI-DOT-NEXT: fmov w0, s0
6370-
; CHECK-GI-DOT-NEXT: ret
6308+
; CHECK-LABEL: add_pair_v8i16_v4i32_double_sext_zext_shuffle:
6309+
; CHECK: // %bb.0: // %entry
6310+
; CHECK-NEXT: uaddlp v1.4s, v1.8h
6311+
; CHECK-NEXT: uaddlp v3.4s, v3.8h
6312+
; CHECK-NEXT: uadalp v1.4s, v0.8h
6313+
; CHECK-NEXT: uadalp v3.4s, v2.8h
6314+
; CHECK-NEXT: add v0.4s, v3.4s, v1.4s
6315+
; CHECK-NEXT: addv s0, v0.4s
6316+
; CHECK-NEXT: fmov w0, s0
6317+
; CHECK-NEXT: ret
63716318
entry:
63726319
%axx = zext <8 x i16> %ax to <8 x i32>
63736320
%s1h = shufflevector <8 x i32> %axx, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>

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