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[AIEX] Add a Pass to expand unallocated 2D/3D into individual ones
If we don't need a full register, we can expand to individual lanes. Co-Authored-By: Krishnam Tibrewala <[email protected]>
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11 files changed

+242
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lines changed

‎llvm/lib/Target/AIE/AIE.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ MachineFunctionPass *createAIEEliminateDuplicatePHI();
6060
FunctionPass *createAIEOutlineMemoryGEP();
6161
FunctionPass *createAIESuperRegRewriter();
6262
FunctionPass *createAIEWawRegRewriter();
63+
FunctionPass *createAIEUnallocatedSuperRegRewriter();
6364
FunctionPass *createAIEPostSelectOptimize();
6465
MachineFunctionPass *
6566
createDeadMachineInstructionElim(bool KeepLifetimeInstructions);
@@ -84,6 +85,8 @@ extern char &AIESuperRegRewriterID;
8485
void initializeAIESuperRegRewriterPass(PassRegistry &);
8586
extern char &AIEWawRegRewriterID;
8687
void initializeAIEWawRegRewriterPass(PassRegistry &);
88+
extern char &AIEUnallocatedSuperRegRewriterID;
89+
void initializeAIEUnallocatedSuperRegRewriterPass(PassRegistry &);
8790
extern char &AIEOutlineMemoryGEPID;
8891
void initializeAIEOutlineMemoryGEPPass(PassRegistry &);
8992

‎llvm/lib/Target/AIE/AIESuperRegUtils.cpp‎

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -154,15 +154,21 @@ void rewriteSuperReg(Register Reg, Register AssignedPhysReg,
154154
LiveRegMatrix &LRM, LiveIntervals &LIS,
155155
SlotIndexes &Indexes, LiveDebugVariables &DebugVars) {
156156
LLVM_DEBUG(dbgs() << "Rewriting " << printReg(Reg, &TRI, 0, &MRI) << '\n');
157-
auto *TII = static_cast<const AIEBaseInstrInfo *>(
158-
VRM.getMachineFunction().getSubtarget().getInstrInfo());
157+
MachineFunction &MF = VRM.getMachineFunction();
158+
auto *TII =
159+
static_cast<const AIEBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
160+
161+
const bool IsAllocated = AssignedPhysReg.isValid();
159162

160163
// Collect all the subreg indices to rewrite as independent vregs.
161164
SmallMapVector<int, Register, 8> SubRegToVReg;
162165
const TargetRegisterClass *SuperRC = MRI.getRegClass(Reg);
163166
assert(!SubRegs.empty());
164167
for (int SubReg : SubRegs) {
165-
const TargetRegisterClass *SubRC = TRI.getSubRegisterClass(SuperRC, SubReg);
168+
const TargetRegisterClass *SubRC =
169+
IsAllocated ? TRI.getSubRegisterClass(SuperRC, SubReg)
170+
: TRI.getLargestLegalSuperClass(
171+
TRI.getSubRegisterClass(SuperRC, SubReg), MF);
166172
SubRegToVReg[SubReg] = MRI.createVirtualRegister(SubRC);
167173
}
168174

@@ -201,7 +207,6 @@ void rewriteSuperReg(Register Reg, Register AssignedPhysReg,
201207
LIS.removeInterval(Reg);
202208

203209
for (auto &[SubRegIdx, VReg] : SubRegToVReg) {
204-
MCRegister SubPhysReg = TRI.getSubReg(AssignedPhysReg, SubRegIdx);
205210
LiveInterval &SubRegLI = LIS.getInterval(VReg);
206211
LLVM_DEBUG(dbgs() << " Assigning Range: " << SubRegLI << '\n');
207212

@@ -212,10 +217,13 @@ void rewriteSuperReg(Register Reg, Register AssignedPhysReg,
212217
LIComponents.push_back(&SubRegLI);
213218
VRM.grow();
214219

215-
for (LiveInterval *LI : LIComponents) {
216-
LRM.assign(*LI, SubPhysReg);
217-
VRM.setRequiredPhys(LI->reg(), SubPhysReg);
218-
LLVM_DEBUG(dbgs() << " Assigned " << printReg(LI->reg()) << "\n");
220+
if (IsAllocated) {
221+
MCRegister SubPhysReg = TRI.getSubReg(AssignedPhysReg, SubRegIdx);
222+
for (LiveInterval *LI : LIComponents) {
223+
LRM.assign(*LI, SubPhysReg);
224+
VRM.setRequiredPhys(LI->reg(), SubPhysReg);
225+
LLVM_DEBUG(dbgs() << " Assigned " << printReg(LI->reg()) << "\n");
226+
}
219227
}
220228
}
221229

‎llvm/lib/Target/AIE/AIEUnallocatedSuperRegRewriter.cpp‎

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
1+
//===----- AIEUnallocatedSuperRegRewriter.cpp - Constrain tied sub-registers
2+
//---------===//
3+
//
4+
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
5+
// See https://llvm.org/LICENSE.txt for license information.
6+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7+
//
8+
// (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
9+
//
10+
//===----------------------------------------------------------------------===//
11+
12+
#include "AIEBaseInstrInfo.h"
13+
#include "AIEBaseRegisterInfo.h"
14+
#include "AIESuperRegUtils.h"
15+
16+
#include "llvm/ADT/MapVector.h"
17+
#include "llvm/ADT/SmallSet.h"
18+
#include "llvm/CodeGen/LiveDebugVariables.h"
19+
#include "llvm/CodeGen/LiveIntervals.h"
20+
#include "llvm/CodeGen/LiveRegMatrix.h"
21+
#include "llvm/CodeGen/LiveStacks.h"
22+
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
23+
#include "llvm/CodeGen/MachineFunction.h"
24+
#include "llvm/CodeGen/MachineFunctionPass.h"
25+
#include "llvm/CodeGen/MachineInstr.h"
26+
#include "llvm/CodeGen/MachineInstrBuilder.h"
27+
#include "llvm/CodeGen/MachineOperand.h"
28+
#include "llvm/CodeGen/MachineRegisterInfo.h"
29+
#include "llvm/CodeGen/Passes.h"
30+
#include "llvm/CodeGen/SlotIndexes.h"
31+
#include "llvm/CodeGen/TargetInstrInfo.h"
32+
#include "llvm/CodeGen/TargetSubtargetInfo.h"
33+
#include "llvm/CodeGen/VirtRegMap.h"
34+
#include "llvm/Support/Debug.h"
35+
#include "llvm/Support/raw_ostream.h"
36+
37+
using namespace llvm;
38+
39+
#define DEBUG_TYPE "aie-ra-prepare"
40+
41+
namespace {
42+
43+
using RegRewriteInfo = std::vector<std::pair<Register, SmallSet<int, 8>>>;
44+
45+
/// Split large unallocated compound registers into multiple new smaller vregs
46+
/// Than can be allocated to scalar registers.
47+
class AIEUnallocatedSuperRegRewriter : public MachineFunctionPass {
48+
49+
public:
50+
static char ID;
51+
AIEUnallocatedSuperRegRewriter() : MachineFunctionPass(ID) {}
52+
53+
void getAnalysisUsage(AnalysisUsage &AU) const override {
54+
AU.setPreservesCFG();
55+
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
56+
AU.addRequired<VirtRegMapWrapperLegacy>();
57+
AU.addPreserved<VirtRegMapWrapperLegacy>();
58+
AU.addRequired<SlotIndexesWrapperPass>();
59+
AU.addPreserved<SlotIndexesWrapperPass>();
60+
AU.addRequired<LiveDebugVariablesWrapperLegacy>();
61+
AU.addPreserved<LiveDebugVariablesWrapperLegacy>();
62+
AU.addRequired<LiveStacksWrapperLegacy>();
63+
AU.addPreserved<LiveStacksWrapperLegacy>();
64+
AU.addRequired<LiveIntervalsWrapperPass>();
65+
AU.addPreserved<LiveIntervalsWrapperPass>();
66+
AU.addRequired<LiveRegMatrixWrapperLegacy>();
67+
AU.addPreserved<LiveRegMatrixWrapperLegacy>();
68+
MachineFunctionPass::getAnalysisUsage(AU);
69+
}
70+
71+
bool runOnMachineFunction(MachineFunction &Fn) override;
72+
};
73+
74+
static RegRewriteInfo getRewriteCandidates(MachineRegisterInfo &MRI,
75+
const AIEBaseRegisterInfo &TRI,
76+
VirtRegMap &VRM) {
77+
RegRewriteInfo RegistersToRewrite;
78+
for (unsigned VRegIdx = 0, End = MRI.getNumVirtRegs(); VRegIdx != End;
79+
++VRegIdx) {
80+
const Register Reg = Register::index2VirtReg(VRegIdx);
81+
82+
// Ignore un-used registers
83+
if (MRI.reg_nodbg_empty(Reg) || VRM.hasPhys(Reg))
84+
continue;
85+
86+
SmallSet<int, 8> RewritableSubRegs =
87+
AIESuperRegUtils::getRewritableSubRegs(Reg, MRI, TRI);
88+
89+
if (RewritableSubRegs.empty())
90+
continue;
91+
92+
LLVM_DEBUG(dbgs() << "Candidate " << printReg(Reg, &TRI, 0, &MRI) << ":"
93+
<< printRegClassOrBank(Reg, MRI, &TRI) << '\n');
94+
95+
RegistersToRewrite.push_back({Reg, RewritableSubRegs});
96+
}
97+
return RegistersToRewrite;
98+
}
99+
100+
void rewriteCandidates(RegRewriteInfo &RegistersToRewrite,
101+
MachineRegisterInfo &MRI, const AIEBaseRegisterInfo &TRI,
102+
VirtRegMap &VRM, LiveRegMatrix &LRM, LiveIntervals &LIS,
103+
SlotIndexes &Indexes, LiveDebugVariables &DebugVars) {
104+
105+
for (auto [VReg, SubRegs] : RegistersToRewrite) {
106+
const MCRegister TempPhysReg;
107+
AIESuperRegUtils::rewriteSuperReg(VReg, TempPhysReg, SubRegs, MRI, TRI, VRM,
108+
LRM, LIS, Indexes, DebugVars);
109+
}
110+
}
111+
112+
bool AIEUnallocatedSuperRegRewriter::runOnMachineFunction(MachineFunction &MF) {
113+
LLVM_DEBUG(llvm::dbgs() << "*** Splitting unallocated super-registers: "
114+
<< MF.getName() << " ***\n");
115+
116+
MachineRegisterInfo &MRI = MF.getRegInfo();
117+
VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
118+
LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
119+
LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
120+
SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI();
121+
LiveDebugVariables &DebugVars =
122+
getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
123+
auto &TRI =
124+
*static_cast<const AIEBaseRegisterInfo *>(MRI.getTargetRegisterInfo());
125+
126+
RegRewriteInfo RegistersToRewrite = getRewriteCandidates(MRI, TRI, VRM);
127+
128+
rewriteCandidates(RegistersToRewrite, MRI, TRI, VRM, LRM, LIS, Indexes,
129+
DebugVars);
130+
131+
return !RegistersToRewrite.empty();
132+
}
133+
134+
} // end anonymous namespace
135+
136+
char AIEUnallocatedSuperRegRewriter::ID = 0;
137+
char &llvm::AIEUnallocatedSuperRegRewriterID =
138+
AIEUnallocatedSuperRegRewriter::ID;
139+
140+
INITIALIZE_PASS(AIEUnallocatedSuperRegRewriter,
141+
"aie-unallocated-superreg-rewrite",
142+
"AIE unallocated super-reg rewrite", false, false)
143+
144+
llvm::FunctionPass *llvm::createAIEUnallocatedSuperRegRewriter() {
145+
return new AIEUnallocatedSuperRegRewriter();
146+
}

‎llvm/lib/Target/AIE/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,7 @@ add_llvm_target(AIECodeGen
135135
AIE2TargetMachine.cpp
136136
AIE2TargetTransformInfo.cpp
137137
AIETiedRegOperands.cpp
138+
AIEUnallocatedSuperRegRewriter.cpp
138139
ReservedRegsLICM.cpp
139140
AIEOutlineMemoryGEP.cpp
140141
AIEWawRegRewriter.cpp

‎llvm/lib/Target/AIE/aie1/AIE1TargetMachine.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAIETarget() {
7070
initializeAIESubRegConstrainerPass(*PR);
7171
initializeAIESuperRegRewriterPass(*PR);
7272
initializeAIEWawRegRewriterPass(*PR);
73+
initializeAIEUnallocatedSuperRegRewriterPass(*PR);
7374
initializeAIEOutlineMemoryGEPPass(*PR);
7475
initializeAIEFinalizeBundlePass(*PR);
7576
initializeAIEMachineAlignmentPass(*PR);

‎llvm/lib/Target/AIE/aie2p/AIE2PTargetMachine.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,8 @@ bool AIE2PPassConfig::addRegAssignAndRewriteOptimized() {
124124
addPass(createAIESuperRegRewriter());
125125
addPass(createGreedyRegisterAllocator(onlyAllocate3D2DRegisters));
126126
addPass(createAIESuperRegRewriter());
127+
if (EnableFineGrainedStagedRA)
128+
addPass(createAIEUnallocatedSuperRegRewriter());
127129
}
128130
addPass(createGreedyRegisterAllocator());
129131
if (EnableWAWRegRewrite) {

‎llvm/test/CodeGen/AIE/aie2p/llc-pipeline-aie2p.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -247,6 +247,7 @@
247247
; AIE-O1-NEXT: AIE super-reg rewrite
248248
; AIE-O1-NEXT: Greedy Register Allocator
249249
; AIE-O1-NEXT: AIE super-reg rewrite
250+
; AIE-O1-NEXT: AIE unallocated super-reg rewrite
250251
; AIE-O1-NEXT: Greedy Register Allocator
251252
; AIE-O1-NEXT: AIE waw-reg rewrite
252253
; AIE-O1-NEXT: Greedy Register Allocator
@@ -472,6 +473,7 @@
472473
; AIE-O23-NEXT: AIE super-reg rewrite
473474
; AIE-O23-NEXT: Greedy Register Allocator
474475
; AIE-O23-NEXT: AIE super-reg rewrite
476+
; AIE-O23-NEXT: AIE unallocated super-reg rewrite
475477
; AIE-O23-NEXT: Greedy Register Allocator
476478
; AIE-O23-NEXT: AIE waw-reg rewrite
477479
; AIE-O23-NEXT: Greedy Register Allocator

‎llvm/test/CodeGen/AIE/aie2p/ra/staged-ra-spill.mir‎

Lines changed: 54 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -6,42 +6,68 @@
66
#
77
# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
88

9+
# RUN: llc -O2 -mtriple=aie2p -verify-machineinstrs --aie-staged-ra -start-before=greedy -aie-staged-ra-fine-grained-alloc=false \
10+
# RUN: -stop-after=virtregrewriter %s -o - | FileCheck %s --check-prefix=RA-STAGED
911
# RUN: llc -O2 -mtriple=aie2p -verify-machineinstrs --aie-staged-ra -start-before=greedy -stop-after=virtregrewriter %s -o - \
10-
# RUN: | FileCheck %s --check-prefix=RA
12+
# RUN: | FileCheck %s --check-prefix=RA-STAGEG-FG
1113

12-
# Test what happens the 2D allocation stage needs to spill, and then the
14+
# Test what happens the 2D allocation stage needs to spill, and then the
1315
# last allocation stage needs to spill again to make space for allocating
14-
# %7:edj = MOV_PD_imm10_pseudo 12.
16+
# %7:edj = MOV_PD_imm10_pseudo 12. Please note that in RA-STAGEG-FG
17+
# (FG = fine grained) we can avoid spills by using scalar registers.
1518
---
1619
name: test_spill_2d_last_stage
1720
tracksRegLiveness: true
1821
body: |
1922
bb.1.entry:
2023
liveins: $p0, $p1, $d1, $d2, $d3, $d4, $d5, $d6, $d7
21-
; RA-LABEL: name: test_spill_2d_last_stage
22-
; RA: liveins: $d1, $d2, $d3, $d4, $d5, $d6, $d7, $p0, $p1
23-
; RA-NEXT: {{ $}}
24-
; RA-NEXT: renamable $dn0 = LDA_dms_lda_idx_imm renamable $p1, 0
25-
; RA-NEXT: renamable $m0 = LDA_dms_lda_idx_imm renamable $p1, 4
26-
; RA-NEXT: renamable $dj0 = LDA_dms_lda_idx_imm renamable $p1, 8
27-
; RA-NEXT: ST_D_SPILL renamable $d0, %stack.1, implicit $sp :: (store (s128) into %stack.1, align 4)
28-
; RA-NEXT: renamable $dj0 = MOV_PD_imm11_pseudo 12
29-
; RA-NEXT: renamable $r0 = LDA_dms_lda_idx renamable $p1, killed renamable $dj0
30-
; RA-NEXT: renamable $d0 = LDA_D_SPILL %stack.1, implicit $sp :: (load (s128) from %stack.1, align 4)
31-
; RA-NEXT: renamable $dc0 = COPY killed renamable $r0
32-
; RA-NEXT: ST_D_SPILL killed renamable $d0, %stack.1, implicit $sp :: (store (s128) into %stack.1, align 4)
33-
; RA-NEXT: renamable $dn0 = LDA_dms_lda_idx_imm renamable $p1, 16
34-
; RA-NEXT: renamable $m0 = LDA_dms_lda_idx_imm renamable $p1, 20
35-
; RA-NEXT: renamable $dj0 = LDA_dms_lda_idx_imm renamable $p1, 24
36-
; RA-NEXT: renamable $dc0 = LDA_dms_lda_idx_imm killed renamable $p1, 28
37-
; RA-NEXT: ST_D_SPILL killed renamable $d0, %stack.0, implicit $sp :: (store (s128) into %stack.0, align 4)
38-
; RA-NEXT: renamable $d0 = LDA_D_SPILL %stack.1, implicit $sp :: (load (s128) from %stack.1, align 4)
39-
; RA-NEXT: $p0, $dc0 = PADDA_2D_split killed $p0, killed $m0, killed $dn0, killed $dj0, killed $dc0
40-
; RA-NEXT: ST_D_SPILL renamable $d0, %stack.1, implicit $sp :: (store (s128) into %stack.1, align 4)
41-
; RA-NEXT: renamable $d0 = LDA_D_SPILL %stack.0, implicit $sp :: (load (s128) from %stack.0, align 4)
42-
; RA-NEXT: $p0, dead $dc0 = PADDA_2D_split killed $p0, killed $m0, killed $dn0, killed $dj0, killed $dc0
43-
; RA-NEXT: renamable $d0 = LDA_D_SPILL %stack.1, implicit $sp :: (load (s128) from %stack.1, align 4)
44-
; RA-NEXT: PseudoRET implicit $lr, implicit killed renamable $p0, implicit killed renamable $dc0, implicit $d1, implicit $d2, implicit $d3, implicit $d4, implicit $d5, implicit $d6, implicit $d7
24+
; RA-STAGED-LABEL: name: test_spill_2d_last_stage
25+
; RA-STAGED: liveins: $d1, $d2, $d3, $d4, $d5, $d6, $d7, $p0, $p1
26+
; RA-STAGED-NEXT: {{ $}}
27+
; RA-STAGED-NEXT: renamable $dn0 = LDA_dms_lda_idx_imm renamable $p1, 0
28+
; RA-STAGED-NEXT: renamable $m0 = LDA_dms_lda_idx_imm renamable $p1, 4
29+
; RA-STAGED-NEXT: renamable $dj0 = LDA_dms_lda_idx_imm renamable $p1, 8
30+
; RA-STAGED-NEXT: ST_D_SPILL renamable $d0, %stack.0, implicit $sp :: (store (s128) into %stack.0, align 4)
31+
; RA-STAGED-NEXT: renamable $dj0 = MOV_PD_imm11_pseudo 12
32+
; RA-STAGED-NEXT: renamable $r0 = LDA_dms_lda_idx renamable $p1, killed renamable $dj0
33+
; RA-STAGED-NEXT: renamable $d0 = LDA_D_SPILL %stack.0, implicit $sp :: (load (s128) from %stack.0, align 4)
34+
; RA-STAGED-NEXT: renamable $dc0 = COPY killed renamable $r0
35+
; RA-STAGED-NEXT: ST_D_SPILL killed renamable $d0, %stack.0, implicit $sp :: (store (s128) into %stack.0, align 4)
36+
; RA-STAGED-NEXT: renamable $dn0 = LDA_dms_lda_idx_imm renamable $p1, 16
37+
; RA-STAGED-NEXT: renamable $m0 = LDA_dms_lda_idx_imm renamable $p1, 20
38+
; RA-STAGED-NEXT: renamable $dj0 = LDA_dms_lda_idx_imm renamable $p1, 24
39+
; RA-STAGED-NEXT: renamable $dc0 = LDA_dms_lda_idx_imm killed renamable $p1, 28
40+
; RA-STAGED-NEXT: ST_D_SPILL killed renamable $d0, %stack.1, implicit $sp :: (store (s128) into %stack.1, align 4)
41+
; RA-STAGED-NEXT: renamable $d0 = LDA_D_SPILL %stack.0, implicit $sp :: (load (s128) from %stack.0, align 4)
42+
; RA-STAGED-NEXT: $p0, $dc0 = PADDA_2D_split killed $p0, $m0, $dn0, $dj0, $dc0
43+
; RA-STAGED-NEXT: ST_D_SPILL killed renamable $d0, %stack.0, implicit $sp :: (store (s128) into %stack.0, align 4)
44+
; RA-STAGED-NEXT: renamable $d0 = LDA_D_SPILL %stack.1, implicit $sp :: (load (s128) from %stack.1, align 4)
45+
; RA-STAGED-NEXT: $p0, dead $dc0 = PADDA_2D_split killed $p0, $m0, $dn0, $dj0, $dc0
46+
; RA-STAGED-NEXT: renamable $d0 = LDA_D_SPILL %stack.0, implicit $sp :: (load (s128) from %stack.0, align 4)
47+
; RA-STAGED-NEXT: PseudoRET implicit $lr, implicit killed renamable $p0, implicit killed renamable $dc0, implicit $d1, implicit $d2, implicit $d3, implicit $d4, implicit $d5, implicit $d6, implicit $d7
48+
;
49+
; RA-STAGEG-FG-LABEL: name: test_spill_2d_last_stage
50+
; RA-STAGEG-FG: liveins: $d1, $d2, $d3, $d4, $d5, $d6, $d7, $p0, $p1
51+
; RA-STAGEG-FG-NEXT: {{ $}}
52+
; RA-STAGEG-FG-NEXT: renamable $dn0 = LDA_dms_lda_idx_imm renamable $p1, 0
53+
; RA-STAGEG-FG-NEXT: renamable $m0 = LDA_dms_lda_idx_imm renamable $p1, 4
54+
; RA-STAGEG-FG-NEXT: renamable $r0 = LDA_dms_lda_idx_imm renamable $p1, 8
55+
; RA-STAGEG-FG-NEXT: renamable $dj0 = MOV_PD_imm11_pseudo 12
56+
; RA-STAGEG-FG-NEXT: renamable $r1 = LDA_dms_lda_idx renamable $p1, killed renamable $dj0
57+
; RA-STAGEG-FG-NEXT: renamable $dc0 = COPY killed renamable $r1
58+
; RA-STAGEG-FG-NEXT: renamable $dj0 = COPY killed renamable $r0
59+
; RA-STAGEG-FG-NEXT: renamable $r1 = LDA_dms_lda_idx_imm renamable $p1, 16
60+
; RA-STAGEG-FG-NEXT: renamable $r3 = LDA_dms_lda_idx_imm renamable $p1, 20
61+
; RA-STAGEG-FG-NEXT: renamable $r2 = LDA_dms_lda_idx_imm renamable $p1, 24
62+
; RA-STAGEG-FG-NEXT: renamable $r0 = LDA_dms_lda_idx_imm killed renamable $p1, 28
63+
; RA-STAGEG-FG-NEXT: $p0, $dc0 = PADDA_2D_split killed $p0, killed $m0, killed $dn0, killed $dj0, killed $dc0
64+
; RA-STAGEG-FG-NEXT: renamable $r4 = COPY killed renamable $dc0
65+
; RA-STAGEG-FG-NEXT: renamable $dc0 = COPY killed renamable $r0
66+
; RA-STAGEG-FG-NEXT: renamable $dn0 = COPY killed renamable $r1
67+
; RA-STAGEG-FG-NEXT: renamable $dj0 = COPY killed renamable $r2
68+
; RA-STAGEG-FG-NEXT: renamable $m0 = COPY killed renamable $r3
69+
; RA-STAGEG-FG-NEXT: $p0, dead $dc0 = PADDA_2D_split killed $p0, killed $m0, killed $dn0, killed $dj0, killed $dc0
70+
; RA-STAGEG-FG-NEXT: PseudoRET implicit $lr, implicit killed renamable $p0, implicit killed renamable $r4, implicit $d1, implicit $d2, implicit $d3, implicit $d4, implicit $d5, implicit $d6, implicit $d7
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%20:ep = COPY $p0
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%21:ep = COPY $p1
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undef %100.sub_dim_size:ed = LDA_dms_lda_idx_imm %21, 0
@@ -58,3 +84,4 @@ body: |
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%20:ep, %101.sub_dim_count:ed = PADDA_2D_split %20, %101.sub_mod, %101.sub_dim_size, %101.sub_dim_stride, %101.sub_dim_count
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PseudoRET implicit $lr, implicit %20, implicit %100.sub_dim_count, implicit $d1, implicit $d2, implicit $d3, implicit $d4, implicit $d5, implicit $d6, implicit $d7
6086
...
87+

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