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[AIEX] Add a base test for store recombination
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‎llvm/test/CodeGen/AIE/GlobalISel/combine-seq-stores-memset.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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#
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# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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# See https://llvm.org/LICENSE.txt for license information.
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# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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#
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# (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple aie2 -run-pass=aie2-prelegalizer-combiner %s -verify-machineinstrs -o - | FileCheck %s
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---
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name: combine_to_s16
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: combine_to_s16
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s20)
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; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8), align 4)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 73
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD1]](p0) :: (store (s8))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s8) = G_CONSTANT i8 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s8), %90(p0) :: (store (s8), align 4)
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%91:_(s20) = G_CONSTANT i20 73
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %82(s8), %92(p0) :: (store (s8))
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PseudoRET implicit $lr
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...
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---
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name: combine_to_s32
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: combine_to_s32
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s20)
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; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD]](p0) :: (store (s16), align 4)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 74
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD1]](p0) :: (store (s16))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s16) = G_CONSTANT i16 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s16), %90(p0) :: (store (s16), align 4)
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%91:_(s20) = G_CONSTANT i20 74
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %82(s16), %92(p0) :: (store (s16))
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PseudoRET implicit $lr
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...
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---
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name: combine_to_s32_mixed
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: combine_to_s32_mixed
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8), align 4)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s20) = G_CONSTANT i20 73
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C3]](s20)
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; CHECK-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16))
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(s20) = G_CONSTANT i20 75
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s20)
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; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD2]](p0) :: (store (s8))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s8) = G_CONSTANT i8 0
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%13:_(s16) = G_CONSTANT i16 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s8), %90(p0) :: (store (s8), align 4)
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%91:_(s20) = G_CONSTANT i20 73
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %13(s16), %92(p0) :: (store (s16))
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%95:_(s20) = G_CONSTANT i20 75
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%96:_(p0) = nuw G_PTR_ADD %84, %95(s20)
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G_STORE %82(s8), %96(p0) :: (store (s8))
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PseudoRET implicit $lr
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...
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---
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name: combine_to_vector
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: combine_to_vector
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s20) = G_CONSTANT i20 80
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD]](p0) :: (store (s32), align 16)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 84
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD1]](p0) :: (store (s32))
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s20) = G_CONSTANT i20 88
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C3]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD2]](p0) :: (store (s32), align 8)
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(s20) = G_CONSTANT i20 92
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; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD3]](p0) :: (store (s32))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%193:_(s16) = G_CONSTANT i16 0
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%82:_(s8) = G_CONSTANT i8 0
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%85:_(s20) = G_CONSTANT i20 64
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%86:_(p0) = nuw G_PTR_ADD %84, %85(s20)
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%95:_(s20) = G_CONSTANT i20 80
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%96:_(p0) = nuw G_PTR_ADD %84, %95(s20)
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G_STORE %0(s32), %96(p0) :: (store (s32), align 16)
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%97:_(s20) = G_CONSTANT i20 84
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%98:_(p0) = nuw G_PTR_ADD %84, %97(s20)
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G_STORE %0(s32), %98(p0) :: (store (s32))
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%99:_(s20) = G_CONSTANT i20 88
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%100:_(p0) = nuw G_PTR_ADD %84, %99(s20)
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G_STORE %0(s32), %100(p0) :: (store (s32), align 8)
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%101:_(s20) = G_CONSTANT i20 92
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%102:_(p0) = nuw G_PTR_ADD %84, %101(s20)
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G_STORE %0(s32), %102(p0) :: (store (s32))
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%103:_(s20) = G_CONSTANT i20 96
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%104:_(p0) = nuw G_PTR_ADD %84, %103(s20)
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PseudoRET implicit $lr
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...
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---
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name: combine_to_vector_leftover
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: combine_to_vector_leftover
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 80
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD]](p0) :: (store (s32), align 16)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s20) = G_CONSTANT i20 84
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C3]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD1]](p0) :: (store (s32))
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; CHECK-NEXT: [[C4:%[0-9]+]]:_(s20) = G_CONSTANT i20 88
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; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C4]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD2]](p0) :: (store (s32), align 8)
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; CHECK-NEXT: [[C5:%[0-9]+]]:_(s20) = G_CONSTANT i20 92
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; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C5]](s20)
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; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD3]](p0) :: (store (s32))
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; CHECK-NEXT: [[C6:%[0-9]+]]:_(s20) = G_CONSTANT i20 96
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; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C6]](s20)
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; CHECK-NEXT: G_STORE [[C1]](s8), [[PTR_ADD4]](p0) :: (store (s8), align 32)
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; CHECK-NEXT: [[C7:%[0-9]+]]:_(s20) = G_CONSTANT i20 97
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; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C7]](s20)
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; CHECK-NEXT: G_STORE [[C1]](s8), [[PTR_ADD5]](p0) :: (store (s8))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%193:_(s16) = G_CONSTANT i16 0
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%82:_(s8) = G_CONSTANT i8 0
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%85:_(s20) = G_CONSTANT i20 64
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%86:_(p0) = nuw G_PTR_ADD %84, %85(s20)
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%95:_(s20) = G_CONSTANT i20 80
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%96:_(p0) = nuw G_PTR_ADD %84, %95(s20)
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G_STORE %0(s32), %96(p0) :: (store (s32), align 16)
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%97:_(s20) = G_CONSTANT i20 84
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%98:_(p0) = nuw G_PTR_ADD %84, %97(s20)
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G_STORE %0(s32), %98(p0) :: (store (s32))
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%99:_(s20) = G_CONSTANT i20 88
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%100:_(p0) = nuw G_PTR_ADD %84, %99(s20)
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G_STORE %0(s32), %100(p0) :: (store (s32), align 8)
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%101:_(s20) = G_CONSTANT i20 92
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%102:_(p0) = nuw G_PTR_ADD %84, %101(s20)
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G_STORE %0(s32), %102(p0) :: (store (s32))
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%103:_(s20) = G_CONSTANT i20 96
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%104:_(p0) = nuw G_PTR_ADD %84, %103(s20)
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G_STORE %82(s8), %104(p0) :: (store (s8), align 32)
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%105:_(s20) = G_CONSTANT i20 97
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%106:_(p0) = nuw G_PTR_ADD %84, %105(s20)
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G_STORE %82(s8), %106(p0) :: (store (s8))
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PseudoRET implicit $lr
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...
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# Negative test cases:
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---
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name: no_combine_avoid_combiner_loop
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: no_combine_avoid_combiner_loop
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8), align 4)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s20) = G_CONSTANT i20 73
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C3]](s20)
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; CHECK-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s6))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s8) = G_CONSTANT i8 0
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%13:_(s16) = G_CONSTANT i16 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s8), %90(p0) :: (store (s8), align 4)
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%91:_(s20) = G_CONSTANT i20 73
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %13(s16), %92(p0) :: (store (s6))
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PseudoRET implicit $lr
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...
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---
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name: no_combine_to_s32_load
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0, $p1
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; CHECK-LABEL: name: no_combine_to_s32_load
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; CHECK: liveins: $p0, $p1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $p1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s20)
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; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD]](p0) :: (store (s16), align 4)
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32))
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 74
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD1]](p0) :: (store (s16))
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; CHECK-NEXT: PseudoRET implicit $lr, implicit [[LOAD]](s32)
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%84:_(p0) = COPY $p0
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%85:_(p0) = COPY $p1
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s16) = G_CONSTANT i16 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s16), %90(p0) :: (store (s16), align 4)
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%4:_(s32) = G_LOAD %85 :: (load (s32))
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%91:_(s20) = G_CONSTANT i20 74
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %82(s16), %92(p0) :: (store (s16))
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PseudoRET implicit $lr, implicit %4
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...
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---
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name: no_combine_to_s32_side_effects
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0, $p1
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; CHECK-LABEL: name: no_combine_to_s32_side_effects
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; CHECK: liveins: $p0, $p1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C1]](s16), [[PTR_ADD]](p0) :: (store (s16), align 4)
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[INT:%[0-9]+]]:_(<32 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aie2p.acc32.v32.I512.ups), [[DEF]](<32 x s16>), [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[C3:%[0-9]+]]:_(s20) = G_CONSTANT i20 74
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C3]](s20)
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; CHECK-NEXT: G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16))
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; CHECK-NEXT: PseudoRET implicit $lr, implicit [[INT]](<32 x s32>)
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s16) = G_CONSTANT i16 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s16), %90(p0) :: (store (s16), align 4)
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%1:_(<32 x s16>) = G_IMPLICIT_DEF
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%8:_(<32 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aie2p.acc32.v32.I512.ups), %1(<32 x s16>), %0(s32), %0(s32)
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%91:_(s20) = G_CONSTANT i20 74
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %82(s16), %92(p0) :: (store (s16))
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PseudoRET implicit $lr, implicit %8
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...
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---
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name: no_combine_to_s32_non_sequential
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $p0
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; CHECK-LABEL: name: no_combine_to_s32_non_sequential
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; CHECK: liveins: $p0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $p0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s20) = G_CONSTANT i20 72
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; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C1]](s20)
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; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD]](p0) :: (store (s16), align 4)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s20) = G_CONSTANT i20 76
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; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[COPY]], [[C2]](s20)
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; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD1]](p0) :: (store (s16))
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; CHECK-NEXT: PseudoRET implicit $lr
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%84:_(p0) = COPY $p0
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%0:_(s32) = G_CONSTANT i32 0
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%82:_(s16) = G_CONSTANT i16 0
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%89:_(s20) = G_CONSTANT i20 72
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%90:_(p0) = nuw G_PTR_ADD %84, %89(s20)
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G_STORE %82(s16), %90(p0) :: (store (s16), align 4)
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%91:_(s20) = G_CONSTANT i20 76
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%92:_(p0) = nuw G_PTR_ADD %84, %91(s20)
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G_STORE %82(s16), %92(p0) :: (store (s16))
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PseudoRET implicit $lr
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...

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