[AIE] Slightly more flexibility in DataDependenceHelper

We pass some flags down which control the asserts that are meant to check
completeness of the scheduler model for postscheduler's sake.
That allows us to create a more approximate ddg in earlier stages.

These would throw, mainly on occurrences of PseudoInstructions

Author: Martien de Jong

llvm/lib/Target/AIE/AIEBaseSubtarget.cpp

@@ -195,6 +195,7 @@ bool updateSuccLatency(SDep &SuccEdge, SUnit &PredSU, int Latency) {
 // The initial graph will have ordering edges induced by hasSideEffects of the
 // locks/DONE.
 class LockDelays : public ScheduleDAGMutation {
+  bool ExactLatencies = true;
   void apply(ScheduleDAGInstrs *DAG) override {
     const auto *TII = static_cast<const AIEBaseInstrInfo *>(DAG->TII);
     const int CoreStallCycle = TII->getCoreStallCycleAfterLock();
@@ -218,22 +219,31 @@ class LockDelays : public ScheduleDAGMutation {
           continue;
         }
         // Ensure memory operation happens before the core stalls
-        int Delay = *TII->getLastMemoryCycle(LdSt->getDesc().SchedClass) -
-                    CoreStallCycle + 1;
+        auto OptLastMemCycle =
+            TII->getLastMemoryCycle(LdSt->getDesc().SchedClass);
+        assert(!ExactLatencies || OptLastMemCycle);
+        const int LastMemCycle = OptLastMemCycle.value_or(7);
+        const int Delay = LastMemCycle - CoreStallCycle + 1;
         updatePredLatency(PredEdge, SU, Delay);
       }
       for (auto &SuccEdge : SU.Succs) {
         MachineInstr *LdSt = SuccEdge.getSUnit()->getInstr();
         if (SuccEdge.getKind() != SDep::Order || !LdSt->mayLoadOrStore()) {
           continue;
         }
+        auto OptFirstMemCycle =
+            TII->getFirstMemoryCycle(LdSt->getDesc().SchedClass);
+        assert(!ExactLatencies || OptFirstMemCycle);
+        const int FirstMemCycle = OptFirstMemCycle.value_or(4);
         // Ensure memory operation happens after the core resumes
-        int Delay = CoreResumeCycle -
-                    *TII->getFirstMemoryCycle(LdSt->getDesc().SchedClass) + 1;
+        const int Delay = CoreResumeCycle - FirstMemCycle + 1;
         updateSuccLatency(SuccEdge, SU, Delay);
       }
     }
-  };
+  }
+
+public:
+  LockDelays(bool ExactLatencies) : ExactLatencies(ExactLatencies) {};
 };
 
 #undef DEBUG_TYPE
@@ -649,6 +659,7 @@ class PropagateIncomingLatencies : public ScheduleDAGMutation {
 /// fix the latencies to preserve the ordering.
 /// E.g. in AIE2: VST.SRS stores in E7, while VLDA reads in E5.
 class MemoryEdges : public ScheduleDAGMutation {
+  bool ExactLatencies = true;
   void apply(ScheduleDAGInstrs *DAG) override {
     const auto *TII = static_cast<const AIEBaseInstrInfo *>(DAG->TII);
     // Run over all instructions that may load or store, and correct the
@@ -677,16 +688,22 @@ class MemoryEdges : public ScheduleDAGMutation {
         // Get the correct latency from the Sched model.
         std::optional<int> MemLat = TII->getMemoryLatency(
             SrcMI.getDesc().getSchedClass(), MI.getDesc().getSchedClass());
-        if (!MemLat.has_value()) {
+        int Latency = 1;
+        if (MemLat.has_value()) {
+          Latency = *MemLat;
+        } else if (ExactLatencies) {
           LLVM_DEBUG(llvm::dbgs()
                      << "Error: no memory latency info for dependency\n  from: "
                      << SrcMI << "    to: " << MI);
           report_fatal_error("Missing memory latency info.");
         }
-        updatePredLatency(PredEdge, SU, *MemLat);
+        updatePredLatency(PredEdge, SU, Latency);
       }
     }
-  };
+  }
+
+public:
+  MemoryEdges(bool ExactLatencies) : ExactLatencies(ExactLatencies) {};
 };
 
 void dumpDependencies(ScheduleDAGInstrs *DAG, SDep::Kind depType,
@@ -865,12 +882,12 @@ class WAWStickyRegistersEdges : public ScheduleDAGMutation {
 std::vector<std::unique_ptr<ScheduleDAGMutation>>
 AIEBaseSubtarget::getPostRAMutationsImpl(const Triple &TT) {
   std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
-  Mutations.emplace_back(std::make_unique<LockDelays>());
+  Mutations.emplace_back(std::make_unique<LockDelays>(true));
   if (!TT.isAIE1()) {
     if (EnableWAWStickyRegisters)
       Mutations.emplace_back(std::make_unique<WAWStickyRegistersEdges>());
     Mutations.emplace_back(std::make_unique<RegionEndEdges>());
-    Mutations.emplace_back(std::make_unique<MemoryEdges>());
+    Mutations.emplace_back(std::make_unique<MemoryEdges>(true));
     Mutations.emplace_back(std::make_unique<MachineSchedWAWEdges>());
     Mutations.emplace_back(std::make_unique<BiasDepth>());
     Mutations.emplace_back(std::make_unique<EmitFixedSUnits>());
@@ -880,12 +897,12 @@ AIEBaseSubtarget::getPostRAMutationsImpl(const Triple &TT) {
 
 // List the Mutations that apply to the interblock DAG construction.
 std::vector<std::unique_ptr<ScheduleDAGMutation>>
-AIEBaseSubtarget::getInterBlockMutationsImpl(const Triple &TT) {
+AIEBaseSubtarget::getDDGMutationsImpl(const Triple &TT, bool ExactLatencies) {
   std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
-  Mutations.emplace_back(std::make_unique<LockDelays>());
+  Mutations.emplace_back(std::make_unique<LockDelays>(ExactLatencies));
   if (!TT.isAIE1()) {
     Mutations.emplace_back(std::make_unique<RegionEndEdges>());
-    Mutations.emplace_back(std::make_unique<MemoryEdges>());
+    Mutations.emplace_back(std::make_unique<MemoryEdges>(ExactLatencies));
     Mutations.emplace_back(std::make_unique<MachineSchedWAWEdges>());
   }
   return Mutations;

llvm/lib/Target/AIE/AIEBaseSubtarget.h

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -77,7 +77,7 @@ class AIEBaseSubtarget {
 
   /// Required DAG mutations for InterBlock dependence analysis
   static std::vector<std::unique_ptr<ScheduleDAGMutation>>
-  getInterBlockMutationsImpl(const Triple &TT);
+  getDDGMutationsImpl(const Triple &TT, bool ExactLatencies);
 
   /// Required DAG mutations during Pre-RA scheduling.
   static std::vector<std::unique_ptr<ScheduleDAGMutation>>

llvm/lib/Target/AIE/AIEDataDependenceHelper.cpp

@@ -21,14 +21,15 @@ static cl::opt<bool>
             cl::desc("Allow memory dependences in DataDependenceHelper "));
 
 DataDependenceHelper::DataDependenceHelper(const MachineSchedContext &Context,
-                                           bool AddMutators)
+                                           bool AddMutators,
+                                           bool ExactLatencies)
     : ScheduleDAGInstrs(*Context.MF, Context.MLI), Context(Context) {
   if (!AddMutators)
     return;
 
   auto &Subtarget = Context.MF->getSubtarget();
   auto TT = Subtarget.getTargetTriple();
-  for (auto &M : AIEBaseSubtarget::getInterBlockMutationsImpl(TT)) {
+  for (auto &M : AIEBaseSubtarget::getDDGMutationsImpl(TT, ExactLatencies)) {
     Mutations.emplace_back(std::move(M));
   }
 }

llvm/lib/Target/AIE/AIEDataDependenceHelper.h

@@ -39,11 +39,8 @@ class DataDependenceHelper : public ScheduleDAGInstrs {
   bool mayAlias(SUnit *SUa, SUnit *SUb, bool TBAA) override;
 
 public:
-  DataDependenceHelper(const MachineSchedContext &Context,
-                       bool AddMutators = true);
-
-  // After adding the nodes, create the edges, using the order in which the
-  // nodes were added.
+  DataDependenceHelper(const MachineSchedContext &Context, bool AddMutators,
+                       bool ExactLatencies);
   void buildEdges();
 
   // Compute the maximum depth of all nodes. The depth is the earliest cycle

llvm/lib/Target/AIE/AIEInterBlockScheduling.h

@@ -46,7 +46,8 @@ class InterBlockEdges {
   IndexMap SuccMap;
 
 public:
-  InterBlockEdges(const MachineSchedContext &Context) : DDG(Context) {}
+  InterBlockEdges(const MachineSchedContext &Context)
+      : DDG(Context, true, true) {}
 
   /// Add a Node to the DAG.
   void addNode(MachineInstr *);

llvm/lib/Target/AIE/AIEPtrModOptimizer.cpp

@@ -60,7 +60,9 @@ bool AIEPtrModOptimizer::runOnMachineFunction(MachineFunction &MF) {
 
   // To build the edges in the DAG, the reserved Registers have to be freezed
   MRI.freezeReservedRegs();
-  AIE::DataDependenceHelper DAG(Context, /*AddMutators=*/false);
+  const bool AddMutators = false;
+  const bool ExactLatencies = false;
+  AIE::DataDependenceHelper DAG(Context, AddMutators, ExactLatencies);
 
   // Fixme: these combiners should be provided by tablegen
   std::vector<const AIE::GenericCombiner *> Combiners;