[AIE][CodeGenFormat] Compute ConflictBits using all given formats

Separate SlotBits from ConflictBits

Author: Martien de Jong

llvm/include/llvm/Target/CodeGenFormat.td

@@ -45,6 +45,10 @@ class InstSlot<string slotname, int Size, bit isDefault=false>  : Operand<OtherV
   // Namespace.
   bit isDefaultSlot = isDefault;
 
+  // Mark a slot as artificial. This will exclude it from any resource
+  // estimations.
+  bit Artificial = false;
+
   let DecoderMethod = "decode" # SlotName # "Slot";
 }
 

llvm/lib/Target/AIE/AIE2PSlotInclude.td

@@ -21,5 +21,6 @@ let Namespace = "AIE2P" in
     // 64 bit one. 
     def nop_slot     : InstSlot<"Nop", 1> {
         let FieldToFind = "nop";
+        let Artificial = true;
     }
 }

llvm/lib/Target/AIE/AIE2Slots.td

@@ -59,6 +59,7 @@ let Namespace = "AIE2" in
   // 64 bit one. 
   def nop_slot     : InstSlot<"Nop", 1> {
     let FieldToFind = "nop";
+    let Artificial = true;
   }
 }
 

llvm/lib/Target/AIE/MCTargetDesc/AIEMCFormats.h

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 // Utility classes to interface the generated Formats from CodeGenFormat with
@@ -93,18 +93,23 @@ class MCSlotInfo {
   const char *SlotName;
   /// Size of the slot (in bits)
   const unsigned Size;
-  /// Bitset representing the occupancy of the slot
+  /// Bitset representing the occupancy of the slots
   const SlotBits SlotOccupancy;
-  /// Opcode of the NOP inst. attached to the slot
+  /// The closure of SlotOccupancy with the computed exclusions,
+  /// e.g. XM implies X and M
+  const SlotBits ConflictBits;
+  /// Opcode of the NOP instruction attached to the slot
   const unsigned NopOpc;
 
 public:
   constexpr MCSlotInfo(const char *SlotName, unsigned Size, SlotBits Bits,
-                       unsigned NopOpc)
-      : SlotName(SlotName), Size(Size), SlotOccupancy(Bits), NopOpc(NopOpc) {}
+                       SlotBits ConflictBits, unsigned NopOpc)
+      : SlotName(SlotName), Size(Size), SlotOccupancy(Bits),
+        ConflictBits(ConflictBits), NopOpc(NopOpc) {}
 
   const char *getName() const { return SlotName; }
   SlotBits getSlotSet() const { return SlotOccupancy; }
+  SlotBits getConflictSet() const { return ConflictBits; }
   unsigned getNOPOpcode() const { return NopOpc; }
   unsigned getSize() const { return Size; }
 };

llvm/test/TableGen/CodeGenFormat/SlotLogicTests/slot_conflicts.td

@@ -0,0 +1,123 @@
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// Copyright 2025 Advanced Micro Devices, Inc. or its affiliates
+//
+
+// RUN: llvm-tblgen --gen-instr-format -I %p -I %p/../ -I %p/../../../../include %s 2>&1 | FileCheck %s
+
+// This is a minimal check for the computations of the conflict bits.
+// We have the slots A. X, M and XM, which interfere like the
+// corresponding slots on typical AIE architectures.
+// We compute conflicts from the totality of formats, and we should find
+// conflicts
+//  X -> {X, XM},
+//  M -> {M, XM},
+//  XM -> {X, M, XM}
+//  A -> {A}
+// and nothing more.
+
+// CHECK-LABEL:   "X",
+// CHECK-NEXT:  8,
+// CHECK-NEXT:  1,
+// CHECK-NEXT:  5,
+// CHECK-LABEL:  "A",
+// CHECK-NEXT:  10,
+// CHECK-NEXT:  2,
+// CHECK-NEXT:  2,
+// CHECK-LABEL:  "XM",
+// CHECK-NEXT:  18,
+// CHECK-NEXT:  4,
+// CHECK-NEXT:  13,
+// CHECK-LABEL:  "M",
+// CHECK-NEXT:  10,
+// CHECK-NEXT:  8,
+// CHECK-NEXT:  12,
+// CHECK-LABEL:  "nop",
+// CHECK-NEXT:  14,
+// CHECK-NEXT:  16,
+// CHECK-NEXT:  31,
+
+include "llvm/Target/Target.td"
+include "llvm/Target/CodeGenFormat.td"
+
+let Namespace = "TEST" in {
+def nop_slot 	 : InstSlot<"nop", 14> { let Artificial = true; }
+def lda_slot     : InstSlot<"A", 10>;
+def alu_slot     : InstSlot<"X", 8>;
+def mov_slot     : InstSlot<"M", 10>;
+def lng_slot     : InstSlot<"XM", 18>;
+}
+
+
+def TESTInstrInfo : InstrInfo;
+
+def TEST : Target {
+  let InstructionSet = TESTInstrInfo;
+}
+
+def TESTCodeGenFormat : CodeGenFormat {
+  let FormatClassEmitted = "";
+}
+
+let Namespace = "TEST" in
+def default_slot : InstSlot<"default", 0, true>;
+
+class TESTInst<dag outs, dag ins, string opc, string arg, list<dag> pattern>
+    : Instruction, InstFormat
+{
+  let Namespace = "TEST";
+
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString = opc # "\t" # arg;
+  let Pattern = pattern;
+
+  let Slot = default_slot;
+}
+
+class TESTSubInst<dag outs, dag ins>
+    : TESTInst<outs, ins, "", "", []>
+{
+  let isComposite = false;
+}
+
+class TESTFormat<dag outs, dag ins> : TESTInst<outs, ins, "", "", []> {
+  let isComposite = true;
+}
+
+
+class TEST_I32<dag outs, dag ins> : TESTFormat<outs, ins> {
+  field bits<32> Inst;
+  field bits<32> instr32;
+  let Inst = {instr32};
+}
+
+def I32_A_XM : TEST_I32<(outs), (ins lda_slot:$lda, lng_slot:$lng)> {
+  bits<10> lda;
+  bits<18> lng;
+  let instr32 = {lda, lng, 0b1001};
+}
+
+def I32_A_X : TEST_I32<(outs), (ins lda_slot:$lda, alu_slot:$alu)> {
+  bits<10> lda;
+  bits<8> alu;
+  let instr32 = {lda, alu, 0b0000000000, 0b1001};
+}
+
+def I32_X_M : TEST_I32<(outs), (ins alu_slot:$alu, mov_slot:$mov)> {
+  bits<8> alu;
+  bits<10> mov;
+  let instr32 = {0b0000000000, alu, mov, 0b0110};
+}
+
+def I32_A_X_M : TEST_I32<(outs), 
+        (ins lda_slot:$lda, alu_slot:$alu, mov_slot:$mov)> {
+  bits<10> lda;
+  bits<8> alu;
+  bits<10> mov;
+  let instr32 = {lda, alu, mov, 0b1110};
+}
+

llvm/unittests/Target/AIE/BundleTest.cpp

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 
@@ -42,10 +42,10 @@ const VLIWFormat FormatData[] = {
     {0, nullptr, {}, 0, 0}};
 const PacketFormats MyFormats{FormatData};
 
-constexpr MCSlotInfo SlotInfos[4] = {{"ALU", 1, 0b0001, 0},
-                                     {"MV", 1, 0b0010, 0},
-                                     {"ST", 1, 0b0100, 0},
-                                     {"LNG", 1, 0b1000, 0}};
+constexpr MCSlotInfo SlotInfos[4] = {{"ALU", 1, 0b0001, 0b0001, 0},
+                                     {"MV", 1, 0b0010, 0b0010, 0},
+                                     {"ST", 1, 0b0100, 0b0100, 0},
+                                     {"LNG", 1, 0b1000, 0b1000, 0}};
 
 // Stay clear of standard opcodes
 static const int FirstOpcode = 1000;

llvm/utils/TableGen/CodeGenFormat.cpp

@@ -109,6 +109,8 @@ void CodeGenFormat::run(raw_ostream &o) {
 
   assert(Slots.size() != 0 && "no Slot detected");
 
+  computeSlotSets(Slots, InstFormats);
+
   o << "#ifdef GET_FORMATS_SLOTKINDS\n"
        "#undef GET_FORMATS_SLOTKINDS\n\n";
   Slots.emitTargetSlotKindEnum(o);
@@ -207,7 +209,6 @@ void CodeGenFormat::run(raw_ostream &o) {
 
     for (TGInstrLayout &Inst : InstFormats)
       if (Inst.isPacketFormat()) {
-        Inst.computeSlotSet();
         Packets.push_back(&Inst);
       }
 
@@ -244,6 +245,47 @@ void CodeGenFormat::run(raw_ostream &o) {
   }
 }
 
+void CodeGenFormat::computeSlotSets(TGTargetSlots &Slots,
+                                    std::vector<TGInstrLayout> &InstFormats) {
+
+  // The slots accommodated by each format.
+  for (TGInstrLayout &Format : InstFormats) {
+    if (Format.isPacketFormat()) {
+      Format.computeSlotSet();
+    }
+  }
+
+  // The universe of all slots
+  uint64_t AllSlots = 0;
+  for (const auto &[_, Slot] : Slots) {
+    if (Slot.isDefaultSlot() || Slot.isArtificial()) {
+      continue;
+    }
+    AllSlots |= Slot.getSlotBits();
+  }
+
+  // Compute the conflict bits of all slots.
+  for (unsigned S = 0; S < Slots.size(); S++) {
+    // Effectively we check whether a slot cannot be combined with another
+    // slot in any format in which the first is accommodated. We start out
+    // with all slots excluded, and eliminate the exclusion when a format is
+    // encountered that allows both ThisSlot and the exclusion.
+    auto &Slot = Slots.getSlot(S).second;
+    const uint64_t ThisSlot = Slot.getSlotBits();
+    uint64_t Excluded = AllSlots;
+    for (TGInstrLayout &Format : InstFormats) {
+      if (!Format.isPacketFormat()) {
+        continue;
+      }
+      uint64_t SlotSet = Format.getSlotSet();
+      if (SlotSet & ThisSlot) {
+        Excluded &= ~SlotSet & AllSlots;
+      }
+    }
+    Slot.setConflictBits(ThisSlot | Excluded);
+  }
+}
+
 // Retrieve the number of consecutive bits (from BitPos) that are part of the
 // same "variable" (described by "VarName")
 // NOTE0: if the bit at BitPos isn't a variable bit, then we simply return 0
@@ -1093,7 +1135,8 @@ void TGTargetSlots::emitSlotsInfoInstantiation(
       << "  " << TS.getSlotSize()
       << ",\n"
       // Right now, we're using the slot num as SlotSet
-      << "  " << (uint64_t(1) << TS.getNumSlot()) << ",\n"
+      << "  " << TS.getSlotBits() << ",\n"
+      << "  " << TS.getConflictBits() << ",\n"
       << "  " << NOPName << "\n"
       << "},\n";
   }

llvm/utils/TableGen/CodeGenFormat.h

@@ -129,9 +129,11 @@ class CodeGenFormat {
   void run(raw_ostream &o);
 
   static unsigned getVariableBits(const std::string &VarName,
-                                  const BitsInit *BI, unsigned posBit);
+                                  const BitsInit *BI, unsigned BitPos);
   static unsigned getFixedBits(std::string &OutChunck, const BitsInit *BI,
-                               unsigned posBit);
+                               unsigned BitPos);
+  static void computeSlotSets(TGTargetSlots &Slots,
+                              std::vector<TGInstrLayout> &InstFormats);
 };
 
 /// Main class abstracting a CodeGenInstruction (CGI).
@@ -269,13 +271,28 @@ class TGTargetSlot {
   std::string SlotName;
   // The namespace of the current instruction
   std::string Namespace;
-  // primarely used when emitting the C++ enumeration constant
+  // primarily used when emitting the C++ enumeration constant
   std::string EnumerationString;
   // Name of the field to find in the hierarchy
   std::string FieldToFind;
+  // Artificial slots should not be considered for resource estimates
+  bool Artificial = false;
   // Unique number attributed (in the pool) for the slot.
   // It is used to generate a unique "SlotSet".
   int NumSlot;
+
+  // The Slot bits for this slot. These are the pristine bits that correspond
+  // to the slots a format accommodates.
+  uint64_t SlotBits = 0;
+
+  // The conflict bits for this slot. These are used to prevent format table
+  // searches as much as possible. It normally duplicates the SlotBit, since
+  // that is a trivial conflict.
+  // However, there may be more bits set. For example, XM conflicts with
+  // XM, X and M.
+  // Note that the scoreboard runs on these conflict bits.
+  uint64_t ConflictBits;
+
   // Size of the Slot, in bits.
   // The storage of the size is made using an integer value as the size could
   // be negative. In this case, the slot pool (TGTargetSlots) will consider
@@ -296,6 +313,7 @@ class TGTargetSlot {
         SlotName(SlotRecord->getValueAsString("SlotName")),
         Namespace(SlotRecord->getValueAsString("Namespace")),
         FieldToFind(SlotRecord->getValueAsString("FieldToFind")),
+        Artificial(SlotRecord->getValueAsBit("Artificial")),
         // NumSlot is defined as -1 for now.
         // When the pool of slots will be finalized, then the final ID will be
         // attributed.
@@ -349,12 +367,21 @@ class TGTargetSlot {
   const std::string &getLabelToFind() const { return FieldToFind; }
 
   unsigned getSlotSize() const { return static_cast<unsigned>(SlotSize); }
+  uint64_t getSlotBits() const { return SlotBits; }
+  uint64_t getConflictBits() const { return ConflictBits; }
 
   const std::string &getEnumerationString() const { return EnumerationString; }
   bool isDefaultSlot() const { return IsDefaultSlot; }
+  bool isArtificial() const { return Artificial; }
+  void setConflictBits(uint64_t Bits) { ConflictBits = Bits; }
 
 private:
-  void setNumSlot(int SlotID) { NumSlot = SlotID; }
+  void setNumSlot(int SlotID) {
+    NumSlot = SlotID;
+    const uint64_t Base = 1;
+    SlotBits = Base << SlotID;
+  }
+
   void setNopInst(const std::string &NOPName) { NOPInstrName = NOPName; }
 };
 
@@ -393,6 +420,8 @@ class TGTargetSlots {
   /// Add the Slot (if legal) in the Slot pool
   bool addSlot(const Record *const R);
 
+  RecordSlot &getSlot(unsigned N) { return Slots[N]; }
+
   /// This method performs a finalization of the slot pool. This finalization
   /// is composed of 2 stages: the attribution of a unique ID for each slot and
   /// then the sorting of the internal container based on their ID, in order to