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konstantinschwarzkonstantinschwarz
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[AIE2P] Add alternative calling convention for library calls
In AIEs default calling convention, all vector registers are caller saved. However, most compiler-rt builtin library functions do not use vector registers. To avoid having to spill vectors to memory in the caller function, we can attach a different calling convention to these library functions.
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13 files changed

+61
-19
lines changed

13 files changed

+61
-19
lines changed

‎llvm/include/llvm/IR/CallingConv.h‎

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@@ -270,6 +270,9 @@ namespace CallingConv {
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/// Preserve X1-X15, X19-X29, SP, Z0-Z31, P0-P15.
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AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1 = 111,
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/// Preserve vector registers.
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AIE_PreserveAll_Vec = 112,
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/// The highest possible ID. Must be some 2^k - 1.
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MaxID = 1023
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};

‎llvm/lib/Target/AIE/AIEBaseISelLowering.cpp‎

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@@ -18,6 +18,7 @@
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#include "MCTargetDesc/AIE2MCTargetDesc.h"
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#include "MCTargetDesc/AIEMCTargetDesc.h"
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#include "MCTargetDesc/aie2p/AIE2PMCTargetDesc.h"
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#include "llvm/IR/RuntimeLibcalls.h"
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#include "llvm/MC/MCRegister.h"
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using namespace llvm;
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‎llvm/lib/Target/AIE/aie2p/AIE2PCallingConv.td‎

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@@ -211,5 +211,12 @@ def CC_AIE2P : CallingConv<[
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def CSR_AIE2P
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: CalleeSavedRegs<(add lr, r8, r9, r10, r11, r12, r13, r14, r15, p6, p7)>;
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def CSR_AIE2P_Vec
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: CalleeSavedRegs<(add lr, r8, r9, r10, r11, r12, r13, r14, r15, p6, p7,
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wl0, wl2, wl4, wl6, wl8, wl10, wl1, wl3, wl5, wl7, wl9, wl11, wh0,
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wh2, wh4, wh6, wh8, wh10, wh1, wh3, wh5, wh7, wh9, wh11, bmll0, bmll1,
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bmll2, bmll3, bmll4, bmhl0, bmhl1, bmhl2, bmhl3, bmhl4, bmlh0, bmlh1,
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bmlh2, bmlh3, bmlh4, bmhh0, bmhh1, bmhh2, bmhh3, bmhh4)>;
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// Needed for implementation of AIERegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;

‎llvm/lib/Target/AIE/aie2p/AIE2PISelLowering.cpp‎

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@@ -21,9 +21,34 @@ using namespace llvm;
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#define DEBUG_TYPE "aie-lower"
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cl::opt<bool>
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VecCCLibcalls("aie-libcalls-preserve-vectors", cl::init(true), cl::Hidden,
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cl::desc("Assume all vector registers are callee-saved by "
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"builtin library functions."));
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AIE2PTargetLowering::AIE2PTargetLowering(const TargetMachine &TM,
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const AIEBaseSubtarget &STI)
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: AIEBaseTargetLowering(TM, STI) {
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if (VecCCLibcalls) {
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setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32,
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CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64,
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CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32,
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CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64,
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CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SREM_I32, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::UREM_I32, CallingConv::AIE_PreserveAll_Vec);
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setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::AIE_PreserveAll_Vec);
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}
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const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
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// We already define in .td which types are legal for each register class.

‎llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.cpp‎

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@@ -25,6 +25,7 @@
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
@@ -285,8 +286,13 @@ AIE2PRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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const uint32_t *
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AIE2PRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID /*CC*/) const {
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return CSR_AIE2P_RegMask;
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CallingConv::ID CC) const {
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switch (CC) {
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case CallingConv::AIE_PreserveAll_Vec:
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return CSR_AIE2P_Vec_RegMask;
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default:
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return CSR_AIE2P_RegMask;
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}
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}
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bool AIE2PRegisterInfo::isTypeLegalForClass(const TargetRegisterClass &RC,

‎llvm/test/CodeGen/AIE/GlobalISel/legalize-sdiv.mir‎

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# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple aie -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=1 %s
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# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2 %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p_vec %s
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---
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name: sdiv_s32

‎llvm/test/CodeGen/AIE/GlobalISel/legalize-sdivrem.mir‎

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# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple aie -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=1 %s
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# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2 %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p_vec %s
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---
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name: sdivrem_s32

‎llvm/test/CodeGen/AIE/GlobalISel/legalize-sitofp.mir‎

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#
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# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2 --check-prefix=COMMON --check-prefix=AIE2 %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p --check-prefix=COMMON --check-prefix=AIE2P %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p_vec --check-prefix=COMMON --check-prefix=AIE2P %s
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---
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name: test_sitofp_s32_to_s32

‎llvm/test/CodeGen/AIE/GlobalISel/legalize-srem.mir‎

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@@ -6,7 +6,7 @@
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# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple aie -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=1 %s
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# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2 %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p_vec %s
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---
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name: srem_s32

‎llvm/test/CodeGen/AIE/GlobalISel/legalize-udiv.mir‎

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# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
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# RUN: llc -mtriple aie -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=1 %s
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# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2 %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p %s
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# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck -DVER=2p_vec %s
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---
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name: udiv_s32

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