Skip to content

Commit 9cf7338

Browse files
F-StuckmannF-Stuckmann
committed
[AIE2P] added VEXT-ZEXT-BCST unit-test
1 parent 647372a commit 9cf7338

File tree

1 file changed

+150
-0
lines changed

1 file changed

+150
-0
lines changed

‎llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-vextbcst.mir‎

Lines changed: 150 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -365,6 +365,32 @@ body: |
365365
PseudoRET implicit $lr, implicit %7(<64 x s8>)
366366
...
367367

368+
---
369+
name: VEXTBCST_8_extract_i32_ZEXT_imm
370+
legalized: true
371+
regBankSelected: true
372+
body: |
373+
bb.1.entry:
374+
liveins: $p0
375+
; CHECK-LABEL: name: VEXTBCST_8_extract_i32_ZEXT_imm
376+
; CHECK: liveins: $p0
377+
; CHECK-NEXT: {{ $}}
378+
; CHECK-NEXT: %ptr:ep = COPY $p0
379+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<64 x s8>))
380+
; CHECK-NEXT: [[VEXTRACT_8_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_imm_vaddSign0 [[VLD_x_idx_imm_pseudo]], 0, implicit $vaddsign0
381+
; CHECK-NEXT: [[VBCST_8_:%[0-9]+]]:vec512 = VBCST_8 [[VEXTRACT_8_vec_extract_imm_vaddSign0_]]
382+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_8_]]
383+
%ptr:ptrregbank(p0) = COPY $p0
384+
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
385+
%2:gprregbank(s32) = G_CONSTANT i32 28
386+
%3:gprregbank(s32) = G_CONSTANT i32 0
387+
%4:vregbank(<64 x s8>) = G_LOAD %ptr(p0) :: (load (<64 x s8>))
388+
%5:gprregbank(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %4(<64 x s8>), %3(s32)
389+
%7:vregbank(<64 x s8>) = G_AIE_BROADCAST_VECTOR %5(s32)
390+
PseudoRET implicit $lr, implicit %7(<64 x s8>)
391+
...
392+
393+
368394
---
369395
name: VEXTBCST_8_extract_i32_r
370396
legalized: true
@@ -390,6 +416,32 @@ body: |
390416
PseudoRET implicit $lr, implicit %7(<64 x s8>)
391417
...
392418

419+
---
420+
name: VEXTBCST_8_extract_i32_ZEXT_r
421+
legalized: true
422+
regBankSelected: true
423+
body: |
424+
bb.1.entry:
425+
liveins: $p0, $r4
426+
; CHECK-LABEL: name: VEXTBCST_8_extract_i32_ZEXT_r
427+
; CHECK: liveins: $p0, $r4
428+
; CHECK-NEXT: {{ $}}
429+
; CHECK-NEXT: %ptr:ep = COPY $p0
430+
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r4
431+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<64 x s8>))
432+
; CHECK-NEXT: [[VEXTRACT_8_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_r_vaddSign0 [[VLD_x_idx_imm_pseudo]], [[COPY]], implicit $vaddsign0
433+
; CHECK-NEXT: [[VBCST_8_:%[0-9]+]]:vec512 = VBCST_8 [[VEXTRACT_8_vec_extract_r_vaddSign0_]]
434+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_8_]]
435+
%ptr:ptrregbank(p0) = COPY $p0
436+
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
437+
%2:gprregbank(s32) = G_CONSTANT i32 28
438+
%3:gprregbank(s32) = COPY $r4
439+
%4:vregbank(<64 x s8>) = G_LOAD %ptr(p0) :: (load (<64 x s8>))
440+
%5:gprregbank(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %4(<64 x s8>), %3(s32)
441+
%7:vregbank(<64 x s8>) = G_AIE_BROADCAST_VECTOR %5(s32)
442+
PseudoRET implicit $lr, implicit %7(<64 x s8>)
443+
...
444+
393445
---
394446
name: VEXTBCST_16_extract_i32_imm
395447
legalized: true
@@ -414,6 +466,31 @@ body: |
414466
PseudoRET implicit $lr, implicit %7(<32 x s16>)
415467
...
416468

469+
---
470+
name: VEXTBCST_16_extract_i32_ZEXT_imm
471+
legalized: true
472+
regBankSelected: true
473+
body: |
474+
bb.1.entry:
475+
liveins: $p0
476+
; CHECK-LABEL: name: VEXTBCST_16_extract_i32_ZEXT_imm
477+
; CHECK: liveins: $p0
478+
; CHECK-NEXT: {{ $}}
479+
; CHECK-NEXT: %ptr:ep = COPY $p0
480+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<32 x s16>))
481+
; CHECK-NEXT: [[VEXTRACT_16_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_imm_vaddSign0 [[VLD_x_idx_imm_pseudo]], 0, implicit $vaddsign0
482+
; CHECK-NEXT: [[VBCST_16_:%[0-9]+]]:vec512 = VBCST_16 [[VEXTRACT_16_vec_extract_imm_vaddSign0_]]
483+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_16_]]
484+
%ptr:ptrregbank(p0) = COPY $p0
485+
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
486+
%2:gprregbank(s32) = G_CONSTANT i32 28
487+
%3:gprregbank(s32) = G_CONSTANT i32 0
488+
%4:vregbank(<32 x s16>) = G_LOAD %ptr(p0) :: (load (<32 x s16>))
489+
%5:gprregbank(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %4(<32 x s16>), %3(s32)
490+
%7:vregbank(<32 x s16>) = G_AIE_BROADCAST_VECTOR %5(s32)
491+
PseudoRET implicit $lr, implicit %7(<32 x s16>)
492+
...
493+
417494
---
418495
name: VEXTBCST_16_extract_i32_r
419496
legalized: true
@@ -439,6 +516,32 @@ body: |
439516
PseudoRET implicit $lr, implicit %7(<32 x s16>)
440517
...
441518

519+
---
520+
name: VEXTBCST_16_extract_i32_ZEXT_r
521+
legalized: true
522+
regBankSelected: true
523+
body: |
524+
bb.1.entry:
525+
liveins: $p0, $r2
526+
; CHECK-LABEL: name: VEXTBCST_16_extract_i32_ZEXT_r
527+
; CHECK: liveins: $p0, $r2
528+
; CHECK-NEXT: {{ $}}
529+
; CHECK-NEXT: %ptr:ep = COPY $p0
530+
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r2
531+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<32 x s16>))
532+
; CHECK-NEXT: [[VEXTRACT_16_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_r_vaddSign0 [[VLD_x_idx_imm_pseudo]], [[COPY]], implicit $vaddsign0
533+
; CHECK-NEXT: [[VBCST_16_:%[0-9]+]]:vec512 = VBCST_16 [[VEXTRACT_16_vec_extract_r_vaddSign0_]]
534+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_16_]]
535+
%ptr:ptrregbank(p0) = COPY $p0
536+
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
537+
%2:gprregbank(s32) = G_CONSTANT i32 28
538+
%3:gprregbank(s32) = COPY $r2
539+
%4:vregbank(<32 x s16>) = G_LOAD %ptr(p0) :: (load (<32 x s16>))
540+
%5:gprregbank(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %4(<32 x s16>), %3(s32)
541+
%7:vregbank(<32 x s16>) = G_AIE_BROADCAST_VECTOR %5(s32)
542+
PseudoRET implicit $lr, implicit %7(<32 x s16>)
543+
...
544+
442545
---
443546
name: VEXTBCST_32_extract_i32_imm
444547
legalized: true
@@ -461,6 +564,29 @@ body: |
461564
PseudoRET implicit $lr, implicit %485(<16 x s32>)
462565
...
463566

567+
---
568+
name: VEXTBCST_32_extract_i32_ZEXT_imm
569+
legalized: true
570+
regBankSelected: true
571+
body: |
572+
bb.1.entry:
573+
liveins: $p0
574+
; CHECK-LABEL: name: VEXTBCST_32_extract_i32_ZEXT_imm
575+
; CHECK: liveins: $p0
576+
; CHECK-NEXT: {{ $}}
577+
; CHECK-NEXT: %ptr:ep = COPY $p0
578+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<16 x s32>))
579+
; CHECK-NEXT: [[VEXTRACT_32_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_32_vec_extract_imm_vaddSign0 [[VLD_x_idx_imm_pseudo]], 0, implicit $vaddsign0
580+
; CHECK-NEXT: [[VBCST_32_:%[0-9]+]]:vec512 = VBCST_32 [[VEXTRACT_32_vec_extract_imm_vaddSign0_]]
581+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_32_]]
582+
%ptr:ptrregbank(p0) = COPY $p0
583+
%4:vregbank(<16 x s32>) = G_LOAD %ptr(p0) :: (load (<16 x s32>))
584+
%483:gprregbank(s32) = G_CONSTANT i32 0
585+
%484:gprregbank(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %4(<16 x s32>), %483(s32)
586+
%485:vregbank(<16 x s32>) = G_AIE_BROADCAST_VECTOR %484(s32)
587+
PseudoRET implicit $lr, implicit %485(<16 x s32>)
588+
...
589+
464590
---
465591
name: VEXTBCST_32_extract_i32_r
466592
legalized: true
@@ -483,3 +609,27 @@ body: |
483609
%485:vregbank(<16 x s32>) = G_AIE_BROADCAST_VECTOR %484(s32)
484610
PseudoRET implicit $lr, implicit %485(<16 x s32>)
485611
...
612+
613+
---
614+
name: VEXTBCST_32_extract_i32_ZEXT_r
615+
legalized: true
616+
regBankSelected: true
617+
body: |
618+
bb.1.entry:
619+
liveins: $p0, $r6
620+
; CHECK-LABEL: name: VEXTBCST_32_extract_i32_ZEXT_r
621+
; CHECK: liveins: $p0, $r6
622+
; CHECK-NEXT: {{ $}}
623+
; CHECK-NEXT: %ptr:ep = COPY $p0
624+
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<16 x s32>))
625+
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r6
626+
; CHECK-NEXT: [[VEXTRACT_32_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_32_vec_extract_r_vaddSign0 [[VLD_x_idx_imm_pseudo]], [[COPY]], implicit $vaddsign0
627+
; CHECK-NEXT: [[VBCST_32_:%[0-9]+]]:vec512 = VBCST_32 [[VEXTRACT_32_vec_extract_r_vaddSign0_]]
628+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_32_]]
629+
%ptr:ptrregbank(p0) = COPY $p0
630+
%4:vregbank(<16 x s32>) = G_LOAD %ptr(p0) :: (load (<16 x s32>))
631+
%483:gprregbank(s32) = COPY $r6
632+
%484:gprregbank(s32) = G_AIE_ZEXT_EXTRACT_VECTOR_ELT %4(<16 x s32>), %483(s32)
633+
%485:vregbank(<16 x s32>) = G_AIE_BROADCAST_VECTOR %484(s32)
634+
PseudoRET implicit $lr, implicit %485(<16 x s32>)
635+
...

0 commit comments

Comments
 (0)