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ValentijnvdBeekValentijnvdBeek
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[AIE2] Implement support for 128-bit vector unmerges
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+150
-21
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3 files changed

+150
-21
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‎llvm/lib/Target/AIE/AIELegalizerInfo.cpp‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -428,9 +428,6 @@ AIELegalizerInfo::AIELegalizerInfo(const AIEBaseSubtarget &ST) {
428428
getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{S64, S32}});
429429
getActionDefinitionsBuilder(G_UNMERGE_VALUES)
430430
.legalFor({{S32, S64}, {S32, V2S32}})
431-
// TODO: can be implemented by unpadding the source vector into Src1,
432-
// shifting and unpadding into Src2
433-
.unsupportedIf(sizeIs(0, 128))
434431
.customIf([=](const LegalityQuery &Query) {
435432
const LLT &DstTy = Query.Types[0];
436433
const LLT &SrcTy = Query.Types[1];
@@ -694,6 +691,16 @@ bool AIELegalizerInfo::legalizeG_UNMERGE_VALUES(LegalizerHelper &Helper,
694691
if (LastTy.getSizeInBits() == 32)
695692
return unpack32BitVector(Helper, MI, LastReg);
696693

694+
// Pad vectors of 128-bit vectors to 256-bit
695+
Register TargetReg = LastReg;
696+
if (LastTy.getSizeInBits() == 128) {
697+
const LLT NewRegTy =
698+
LLT::fixed_vector(LastTy.getNumElements() * 2, LastTy.getScalarType());
699+
const Register NewReg = MRI.createGenericVirtualRegister(NewRegTy);
700+
MIRBuilder.buildInstr(AIE2::G_AIE_PAD_VECTOR_UNDEF, {NewReg}, {LastReg});
701+
TargetReg = NewReg;
702+
}
703+
697704
const unsigned NumOperands = MI.getNumOperands() - 1;
698705
for (unsigned Index = 0; Index < NumOperands; ++Index) {
699706
const Register Current = MI.getOperand(Index).getReg();
@@ -705,7 +712,7 @@ bool AIELegalizerInfo::legalizeG_UNMERGE_VALUES(LegalizerHelper &Helper,
705712
// of the builtin is to create 64-bit constants.
706713
const MachineInstrBuilder CurrentIndex =
707714
MIRBuilder.buildConstant(LLT::scalar(32), Index);
708-
MIRBuilder.buildExtractVectorElement(Current, LastReg, CurrentIndex);
715+
MIRBuilder.buildExtractVectorElement(Current, TargetReg, CurrentIndex);
709716
}
710717

711718
MI.eraseFromParent();

‎llvm/test/CodeGen/AIE/aie2/GlobalISel/legalize-unmerge-values.mir‎

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,3 +386,142 @@ body: |
386386
%7(s32) = G_SEXT %3(s8)
387387
%8(s32) = G_SEXT %4(s8)
388388
PseudoRET implicit $lr, implicit %5, implicit %6, implicit %7, implicit %8
389+
...
390+
---
391+
name: test_unmerge_v8s16
392+
registers:
393+
- { id: 0, class: _, preferred-register: '' }
394+
- { id: 1, class: _, preferred-register: '' }
395+
- { id: 2, class: _, preferred-register: '' }
396+
- { id: 3, class: _, preferred-register: '' }
397+
- { id: 4, class: _, preferred-register: '' }
398+
- { id: 5, class: _, preferred-register: '' }
399+
- { id: 6, class: _, preferred-register: '' }
400+
- { id: 7, class: _, preferred-register: '' }
401+
- { id: 8, class: _, preferred-register: '' }
402+
- { id: 9, class: _, preferred-register: '' }
403+
- { id: 10, class: _, preferred-register: '' }
404+
legalized: false
405+
body: |
406+
bb.0.entry:
407+
liveins: $wl0
408+
; CHECK-LABEL: name: test_unmerge_v8s16
409+
; CHECK: liveins: $wl0
410+
; CHECK-NEXT: {{ $}}
411+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wl0
412+
; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_AIE_UNPAD_VECTOR [[COPY]](<16 x s16>)
413+
; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<16 x s16>) = G_AIE_PAD_VECTOR_UNDEF [[AIE_UNPAD_VECTOR]](<8 x s16>)
414+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
415+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<16 x s16>), [[C]](s32)
416+
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[AIE_SEXT_EXTRACT_VECTOR_ELT]], 16
417+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASSERT_SEXT]], 16
418+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[SEXT_INREG]](s32)
419+
%0:_(<16 x s16>) = COPY $wl0
420+
%10:_(<8 x s16>) = G_AIE_UNPAD_VECTOR %0:_(<16 x s16>)
421+
%1(s16), %2(s16), %3(s16), %4(s16), %5(s16), %6(s16), %7(s16), %8(s16) = G_UNMERGE_VALUES %10(<8 x s16>)
422+
%9(s32) = G_SEXT %4(s16)
423+
PseudoRET implicit $lr, implicit %9
424+
...
425+
---
426+
name: test_unmerge_v4s32
427+
registers:
428+
- { id: 0, class: _, preferred-register: '' }
429+
- { id: 1, class: _, preferred-register: '' }
430+
- { id: 2, class: _, preferred-register: '' }
431+
- { id: 3, class: _, preferred-register: '' }
432+
- { id: 4, class: _, preferred-register: '' }
433+
- { id: 5, class: _, preferred-register: '' }
434+
legalized: false
435+
body: |
436+
bb.0.entry:
437+
liveins: $wl0
438+
; CHECK-LABEL: name: test_unmerge_v4s32
439+
; CHECK: liveins: $wl0
440+
; CHECK-NEXT: {{ $}}
441+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $wl0
442+
; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_AIE_UNPAD_VECTOR [[COPY]](<8 x s32>)
443+
; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<8 x s32>) = G_AIE_PAD_VECTOR_UNDEF [[AIE_UNPAD_VECTOR]](<4 x s32>)
444+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
445+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<8 x s32>), [[C]](s32)
446+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_SEXT_EXTRACT_VECTOR_ELT]](s32)
447+
%0:_(<8 x s32>) = COPY $wl0
448+
%5:_(<4 x s32>) = G_AIE_UNPAD_VECTOR %0:_(<8 x s32>)
449+
%1(s32), %2(s32), %3(s32), %4(s32) = G_UNMERGE_VALUES %5(<4 x s32>)
450+
PseudoRET implicit $lr, implicit %4
451+
...
452+
---
453+
name: test_unmerge_v16s8
454+
registers:
455+
- { id: 0, class: _, preferred-register: '' }
456+
- { id: 1, class: _, preferred-register: '' }
457+
- { id: 2, class: _, preferred-register: '' }
458+
- { id: 3, class: _, preferred-register: '' }
459+
- { id: 4, class: _, preferred-register: '' }
460+
- { id: 5, class: _, preferred-register: '' }
461+
- { id: 6, class: _, preferred-register: '' }
462+
- { id: 7, class: _, preferred-register: '' }
463+
- { id: 8, class: _, preferred-register: '' }
464+
- { id: 9, class: _, preferred-register: '' }
465+
- { id: 10, class: _, preferred-register: '' }
466+
- { id: 11, class: _, preferred-register: '' }
467+
- { id: 12, class: _, preferred-register: '' }
468+
- { id: 13, class: _, preferred-register: '' }
469+
- { id: 14, class: _, preferred-register: '' }
470+
- { id: 15, class: _, preferred-register: '' }
471+
- { id: 16, class: _, preferred-register: '' }
472+
- { id: 17, class: _, preferred-register: '' }
473+
- { id: 18, class: _, preferred-register: '' }
474+
legalized: false
475+
body: |
476+
bb.0.entry:
477+
liveins: $wl0
478+
; CHECK-LABEL: name: test_unmerge_v16s8
479+
; CHECK: liveins: $wl0
480+
; CHECK-NEXT: {{ $}}
481+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wl0
482+
; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_AIE_UNPAD_VECTOR [[COPY]](<32 x s8>)
483+
; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<32 x s8>) = G_AIE_PAD_VECTOR_UNDEF [[AIE_UNPAD_VECTOR]](<16 x s8>)
484+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
485+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<32 x s8>), [[C]](s32)
486+
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[AIE_SEXT_EXTRACT_VECTOR_ELT]], 8
487+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASSERT_SEXT]], 8
488+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[SEXT_INREG]](s32)
489+
%0:_(<32 x s8>) = COPY $wl0
490+
%18:_(<16 x s8>) = G_AIE_UNPAD_VECTOR %0:_(<32 x s8>)
491+
%1(s8), %2(s8), %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8), %9(s8), %10(s8), %11(s8), %12(s8), %13(s8), %14(s8), %15(s8), %16(s8) = G_UNMERGE_VALUES %18(<16 x s8>)
492+
%17(s32) = G_SEXT %4(s8)
493+
PseudoRET implicit $lr, implicit %17
494+
...
495+
---
496+
name: test_unmerge_128bit_order
497+
registers:
498+
- { id: 0, class: _, preferred-register: '' }
499+
- { id: 1, class: _, preferred-register: '' }
500+
- { id: 2, class: _, preferred-register: '' }
501+
- { id: 3, class: _, preferred-register: '' }
502+
- { id: 4, class: _, preferred-register: '' }
503+
- { id: 5, class: _, preferred-register: '' }
504+
legalized: false
505+
body: |
506+
bb.0.entry:
507+
liveins: $wl0
508+
; CHECK-LABEL: name: test_unmerge_128bit_order
509+
; CHECK: liveins: $wl0
510+
; CHECK-NEXT: {{ $}}
511+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $wl0
512+
; CHECK-NEXT: [[AIE_UNPAD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_AIE_UNPAD_VECTOR [[COPY]](<8 x s32>)
513+
; CHECK-NEXT: [[AIE_PAD_VECTOR_UNDEF:%[0-9]+]]:_(<8 x s32>) = G_AIE_PAD_VECTOR_UNDEF [[AIE_UNPAD_VECTOR]](<4 x s32>)
514+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
515+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<8 x s32>), [[C]](s32)
516+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
517+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT1:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<8 x s32>), [[C1]](s32)
518+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
519+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT2:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<8 x s32>), [[C2]](s32)
520+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
521+
; CHECK-NEXT: [[AIE_SEXT_EXTRACT_VECTOR_ELT3:%[0-9]+]]:_(s32) = G_AIE_SEXT_EXTRACT_VECTOR_ELT [[AIE_PAD_VECTOR_UNDEF]](<8 x s32>), [[C3]](s32)
522+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AIE_SEXT_EXTRACT_VECTOR_ELT]](s32), implicit [[AIE_SEXT_EXTRACT_VECTOR_ELT1]](s32), implicit [[AIE_SEXT_EXTRACT_VECTOR_ELT2]](s32), implicit [[AIE_SEXT_EXTRACT_VECTOR_ELT3]](s32)
523+
%0:_(<8 x s32>) = COPY $wl0
524+
%5:_(<4 x s32>) = G_AIE_UNPAD_VECTOR %0:_(<8 x s32>)
525+
%1(s32), %2(s32), %3(s32), %4(s32) = G_UNMERGE_VALUES %5(<4 x s32>)
526+
PseudoRET implicit $lr, implicit %1, implicit %2, implicit %3, implicit %4
527+
...

‎llvm/test/CodeGen/AIE/aie2/GlobalISel/xfail-legalizer-vec128.ll‎

Lines changed: 0 additions & 17 deletions
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