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ValentijnvdBeekValentijnvdBeek
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[AIE2] Rewrite G_CONCAT_VECTOR selection as table-gen
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3 files changed

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‎llvm/lib/Target/AIE/AIE2InstrPatterns.td‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -961,6 +961,22 @@ def : Concat256<int_aie2_concat_512_256_acc, ACC512, ACC256>;
961961
def : Concat512<int_aie2_concat_1024_512_acc, ACC1024, ACC512>;
962962
def : Concat1024<int_aie2_concat_1024_256_acc, ACC1024, ACC256>;
963963

964+
// concat_vector generic opcode
965+
def : Pat<(v16i32 (concat_vectors (v8i32 VEC256:$src0), (v8i32 VEC256:$src1))),
966+
(v16i32 (REG_SEQUENCE VEC512, VEC256:$src0, sub_256_lo, VEC256:$src1, sub_256_hi))>;
967+
def : Pat<(v32i32 (concat_vectors (v16i32 VEC512:$src0), (v16i32 VEC512:$src1))),
968+
(v32i32 (REG_SEQUENCE VEC1024, VEC512:$src0, sub_512_lo, VEC512:$src1, sub_512_hi))>;
969+
970+
def : Pat<(v32i16 (concat_vectors (v16i16 VEC256:$src0), (v16i16 VEC256:$src1))),
971+
(v32i16 (REG_SEQUENCE VEC512, VEC256:$src0, sub_256_lo, VEC256:$src1, sub_256_hi))>;
972+
def : Pat<(v64i16 (concat_vectors (v32i16 VEC512:$src0), (v32i16 VEC512:$src1))),
973+
(v64i16 (REG_SEQUENCE VEC1024, VEC512:$src0, sub_512_lo, VEC512:$src1, sub_512_hi))>;
974+
975+
def : Pat<(v64i8 (concat_vectors (v32i8 VEC256:$src0), (v32i8 VEC256:$src1))),
976+
(v64i8 (REG_SEQUENCE VEC512, VEC256:$src0, sub_256_lo, VEC256:$src1, sub_256_hi))>;
977+
def : Pat<(v128i8 (concat_vectors (v64i8 VEC512:$src0), (v64i8 VEC512:$src1))),
978+
(v128i8 (REG_SEQUENCE VEC1024, VEC512:$src0, sub_512_lo, VEC512:$src1, sub_512_hi))>;
979+
964980
// Extract
965981
def : Pat<(int_aie2_ext_I256_I512 VEC512:$src, 0x0),
966982
(v8i32 (EXTRACT_SUBREG VEC512:$src, sub_256_lo))>;

‎llvm/lib/Target/AIE/AIE2InstructionSelector.cpp‎

Lines changed: 0 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,6 @@ class AIE2InstructionSelector : public InstructionSelector {
142142
bool isWrite);
143143
bool selectG_AIE_ADD_VECTOR_ELT_LEFT(MachineInstr &I,
144144
MachineRegisterInfo &MRI);
145-
bool selectG_CONCAT_VECTORS(MachineInstr &I, MachineRegisterInfo &MRI);
146145
bool selectG_BRCOND(MachineInstr &I, MachineRegisterInfo &MRI);
147146
bool selectG_BRINDIRECT(MachineInstr &I, MachineRegisterInfo &MRI);
148147
bool selectG_JUMP_TABLE(MachineInstr &I, MachineRegisterInfo &MRI);
@@ -742,8 +741,6 @@ bool AIE2InstructionSelector::select(MachineInstr &I) {
742741
return selectG_UNMERGE_VALUES(I, MRI);
743742
case AIE2::G_AIE_ADD_VECTOR_ELT_LEFT:
744743
return selectG_AIE_ADD_VECTOR_ELT_LEFT(I, MRI);
745-
case G_CONCAT_VECTORS:
746-
return selectG_CONCAT_VECTORS(I, MRI);
747744
case AIE2::G_AIE_OFFSET_STORE:
748745
case AIE2::G_AIE_POSTINC_STORE:
749746
case AIE2::G_AIE_POSTINC_2D_STORE:
@@ -843,52 +840,6 @@ bool AIE2InstructionSelector::selectG_AIE_ADD_VECTOR_ELT_LEFT(
843840
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
844841
}
845842

846-
// WIP: Implement this as a tablegen pattern instead, it is very similar to the
847-
// definition used for instrinsics.
848-
bool AIE2InstructionSelector::selectG_CONCAT_VECTORS(MachineInstr &I,
849-
MachineRegisterInfo &MRI) {
850-
const Register DstVecReg = I.getOperand(0).getReg();
851-
const Register Src1VecReg = I.getOperand(1).getReg();
852-
const Register Src2VecReg = I.getOperand(2).getReg();
853-
854-
const unsigned DstVecSize = MRI.getType(DstVecReg).getSizeInBits();
855-
const unsigned Src1VecSize = MRI.getType(Src1VecReg).getSizeInBits();
856-
const unsigned Src2VecSize = MRI.getType(Src2VecReg).getSizeInBits();
857-
858-
assert(
859-
Src1VecSize == Src2VecSize && (DstVecSize == 2 * Src1VecSize) &&
860-
(I.getNumOperands() == 3) &&
861-
"Vectors can only be concatenated if the size of the two operands are "
862-
"the same and are, if added together, equal to the destination vector");
863-
864-
// We are using a Reg Sequence here instead of copies since using
865-
// subregisters causes the SSA violations to occur since it sees %x_hi and
866-
// %x_lo as the same register.
867-
MachineInstrBuilder RegSeq;
868-
const TargetRegisterClass *TRC = nullptr;
869-
if (DstVecSize == 512) {
870-
RegSeq = MIB.buildInstr(AIE2::REG_SEQUENCE, {DstVecReg}, {})
871-
.addReg(Src1VecReg)
872-
.addImm(AIE2::sub_256_lo)
873-
.addReg(Src2VecReg)
874-
.addImm(AIE2::sub_256_hi);
875-
TRC = &AIE2::VEC512RegClass;
876-
} else if (DstVecSize == 1024) {
877-
RegSeq = MIB.buildInstr(AIE2::REG_SEQUENCE, {DstVecReg}, {})
878-
.addReg(Src1VecReg)
879-
.addImm(AIE2::sub_512_lo)
880-
.addReg(Src2VecReg)
881-
.addImm(AIE2::sub_512_hi);
882-
TRC = &AIE2::VEC1024RegClass;
883-
}
884-
885-
constrainOperandRegClass(*MF, TRI, MRI, TII, RBI, *RegSeq, *TRC,
886-
RegSeq->getOperand(0));
887-
888-
I.eraseFromParent();
889-
return true;
890-
}
891-
892843
bool AIE2InstructionSelector::selectG_BRCOND(MachineInstr &I,
893844
MachineRegisterInfo &MRI) {
894845
Register CondReg = I.getOperand(0).getReg();

‎llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-concat-vectors.mir‎

Lines changed: 86 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ stack:
1818
body: |
1919
bb.0.entry:
2020
; CHECK-LABEL: name: vconcat_1024
21-
; CHECK: [[DEF:%[0-9]+]]:vec512 = IMPLICIT_DEF
22-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:vec512 = IMPLICIT_DEF
21+
; CHECK: [[DEF:%[0-9]+]]:exe = IMPLICIT_DEF
22+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:exo = IMPLICIT_DEF
2323
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[DEF]], %subreg.sub_512_lo, [[DEF1]], %subreg.sub_512_hi
2424
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
2525
%0:vregbank(<16 x s32>) = G_IMPLICIT_DEF
@@ -29,20 +29,100 @@ body: |
2929
...
3030

3131
---
32-
name: vconcat_512
32+
name: vconcat_512_32
3333
legalized: true
3434
regBankSelected: true
3535
tracksRegLiveness: true
3636
stack:
3737
- { id: 0, name: "", size: 128, alignment: 32 }
3838
body: |
3939
bb.0.entry:
40-
; CHECK-LABEL: name: vconcat_512
41-
; CHECK: [[DEF:%[0-9]+]]:vec256 = IMPLICIT_DEF
42-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:vec256 = IMPLICIT_DEF
40+
; CHECK-LABEL: name: vconcat_512_32
41+
; CHECK: [[DEF:%[0-9]+]]:ewl = IMPLICIT_DEF
42+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:ewh = IMPLICIT_DEF
4343
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec512 = REG_SEQUENCE [[DEF]], %subreg.sub_256_lo, [[DEF1]], %subreg.sub_256_hi
4444
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
4545
%0:vregbank(<8 x s32>) = G_IMPLICIT_DEF
4646
%1:vregbank(<8 x s32>) = G_IMPLICIT_DEF
4747
%2:vregbank(<16 x s32>) = G_CONCAT_VECTORS %0(<8 x s32>), %1(<8 x s32>)
4848
PseudoRET implicit $lr, implicit %2
49+
...
50+
51+
---
52+
name: vconcat_512_16
53+
legalized: true
54+
regBankSelected: true
55+
tracksRegLiveness: true
56+
stack:
57+
- { id: 0, name: "", size: 128, alignment: 32 }
58+
body: |
59+
bb.0.entry:
60+
; CHECK-LABEL: name: vconcat_512_16
61+
; CHECK: [[DEF:%[0-9]+]]:ewl = IMPLICIT_DEF
62+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:ewh = IMPLICIT_DEF
63+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec512 = REG_SEQUENCE [[DEF]], %subreg.sub_256_lo, [[DEF1]], %subreg.sub_256_hi
64+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
65+
%0:vregbank(<16 x s16>) = G_IMPLICIT_DEF
66+
%1:vregbank(<16 x s16>) = G_IMPLICIT_DEF
67+
%2:vregbank(<32 x s16>) = G_CONCAT_VECTORS %0(<16 x s16>), %1(<16 x s16>)
68+
PseudoRET implicit $lr, implicit %2
69+
...
70+
71+
---
72+
name: vconcat_1024_16
73+
legalized: true
74+
regBankSelected: true
75+
tracksRegLiveness: true
76+
stack:
77+
- { id: 0, name: "", size: 128, alignment: 32 }
78+
body: |
79+
bb.0.entry:
80+
; CHECK-LABEL: name: vconcat_1024_16
81+
; CHECK: [[DEF:%[0-9]+]]:exe = IMPLICIT_DEF
82+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:exo = IMPLICIT_DEF
83+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[DEF]], %subreg.sub_512_lo, [[DEF1]], %subreg.sub_512_hi
84+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
85+
%0:vregbank(<32 x s16>) = G_IMPLICIT_DEF
86+
%1:vregbank(<32 x s16>) = G_IMPLICIT_DEF
87+
%2:vregbank(<64 x s16>) = G_CONCAT_VECTORS %0(<32 x s16>), %1(<32 x s16>)
88+
PseudoRET implicit $lr, implicit %2
89+
...
90+
91+
---
92+
name: vconcat_512_8
93+
legalized: true
94+
regBankSelected: true
95+
tracksRegLiveness: true
96+
stack:
97+
- { id: 0, name: "", size: 128, alignment: 32 }
98+
body: |
99+
bb.0.entry:
100+
; CHECK-LABEL: name: vconcat_512_8
101+
; CHECK: [[DEF:%[0-9]+]]:ewl = IMPLICIT_DEF
102+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:ewh = IMPLICIT_DEF
103+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec512 = REG_SEQUENCE [[DEF]], %subreg.sub_256_lo, [[DEF1]], %subreg.sub_256_hi
104+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
105+
%0:vregbank(<32 x s8>) = G_IMPLICIT_DEF
106+
%1:vregbank(<32 x s8>) = G_IMPLICIT_DEF
107+
%2:vregbank(<64 x s8>) = G_CONCAT_VECTORS %0(<32 x s8>), %1(<32 x s8>)
108+
PseudoRET implicit $lr, implicit %2
109+
...
110+
111+
---
112+
name: vconcat_1024_8
113+
legalized: true
114+
regBankSelected: true
115+
tracksRegLiveness: true
116+
stack:
117+
- { id: 0, name: "", size: 128, alignment: 32 }
118+
body: |
119+
bb.0.entry:
120+
; CHECK-LABEL: name: vconcat_1024_8
121+
; CHECK: [[DEF:%[0-9]+]]:exe = IMPLICIT_DEF
122+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:exo = IMPLICIT_DEF
123+
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[DEF]], %subreg.sub_512_lo, [[DEF1]], %subreg.sub_512_hi
124+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
125+
%0:vregbank(<64 x s8>) = G_IMPLICIT_DEF
126+
%1:vregbank(<64 x s8>) = G_IMPLICIT_DEF
127+
%2:vregbank(<128 x s8>) = G_CONCAT_VECTORS %0(<64 x s8>), %1(<64 x s8>)
128+
PseudoRET implicit $lr, implicit %2

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