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[AIE2P] Extend vector composite register class with fifo registers
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3 files changed

+49
-28
lines changed

3 files changed

+49
-28
lines changed

‎llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -683,52 +683,52 @@ void AIE2PInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
683683
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
684684
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
685685
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
686-
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
687-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
686+
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
687+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
688688
getKillRegState(KillSrc));
689689
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
690-
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
691-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
690+
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
691+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
692692
getKillRegState(KillSrc));
693693
} else if ((AIE2P::VEC1024RegClass.contains(SrcReg)) &&
694694
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
695695
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
696-
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
696+
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
697697
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
698698
getKillRegState(KillSrc));
699699
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
700-
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
700+
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
701701
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
702702
getKillRegState(KillSrc));
703703
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
704704
(AIE2P::VEC1024RegClass.contains(DstReg))) {
705705
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
706706
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
707-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
707+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
708708
getKillRegState(KillSrc));
709709
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
710710
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
711-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
711+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
712712
getKillRegState(KillSrc));
713713
} else if ((AIE2P::ACC1024RegClass.contains(SrcReg)) &&
714714
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
715715
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
716-
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
716+
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
717717
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
718718
getKillRegState(KillSrc));
719719
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
720-
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
720+
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
721721
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
722722
getKillRegState(KillSrc));
723723
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
724724
(AIE2P::ACC1024RegClass.contains(DstReg))) {
725725
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
726726
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
727-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
727+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
728728
getKillRegState(KillSrc));
729729
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
730730
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
731-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
731+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
732732
getKillRegState(KillSrc));
733733
} else if ((AIE2P::eLRegClass.contains(SrcReg)) &&
734734
(AIE2P::EXPVEC64RegClass.contains(DstReg))) {
@@ -1055,8 +1055,8 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
10551055
return {{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_lo},
10561056
{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_hi}};
10571057
case AIE2P::VST_FIFO_SPILL:
1058-
return {{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_lo_fifo},
1059-
{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_hi_fifo}};
1058+
return {{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_512_lo},
1059+
{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_512_hi}};
10601060
case AIE2P::VST_PLFR_SPILL:
10611061
return {{AIE2P::VST_FIFO_SPILL, AIE2P::sub_fifo},
10621062
{AIE2P::ST_dms_sts_spill, AIE2P::sub_avail},
@@ -1092,8 +1092,8 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
10921092
return {{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_lo},
10931093
{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_hi}};
10941094
case AIE2P::VLDA_FIFO_SPILL:
1095-
return {{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_lo_fifo},
1096-
{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_hi_fifo}};
1095+
return {{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_512_lo},
1096+
{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_512_hi}};
10971097
case AIE2P::VLDA_PLFR_SPILL:
10981098
return {
10991099
{AIE2P::VLDA_FIFO_SPILL, AIE2P::sub_fifo},

‎llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2459,7 +2459,7 @@ bool AIE2PInstructionSelector::selectWideG_AIE_LOAD_STORE(
24592459
RC1024 = &AIE2P::VEC1024RegClass;
24602460
} else if (RBID == AIE2P::FifoRegBankID) {
24612461
RC512 = &AIE2P::FIFO512RegClass;
2462-
SubRegIdxes = {AIE2P::sub_lo_fifo, AIE2P::sub_hi_fifo};
2462+
SubRegIdxes = {AIE2P::sub_512_lo, AIE2P::sub_512_hi};
24632463
RC1024 = &AIE2P::FIFO1024RegClass;
24642464
} else {
24652465
llvm_unreachable("Unknown Register Bank ID!");

‎llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.td‎

Lines changed: 32 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -262,21 +262,42 @@ class AIE2PDim3DRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName>
262262
// Core ID
263263
def CORE_ID : AIE2PSPLReg<10, "core_id">;
264264
def mCoreID : AIE2P20BitRegisterClass<(add CORE_ID)>;
265+
266+
let isArtificial = 1 in {
267+
def dummy_sfh_l : AIE2P3BitReg<0, "dummy_sfh_l">;
268+
def dummy_sfh_h : AIE2P3BitReg<0, "dummy_sfh_h">;
269+
def dummy_sfl_l : AIE2P3BitReg<0, "dummy_sfl_l">;
270+
def dummy_sfl_h : AIE2P3BitReg<0, "dummy_sfl_h">;
271+
272+
def dummy_lfh0_l : AIE2P3BitReg<0, "dummy_lfh0_l">;
273+
def dummy_lfh0_h : AIE2P3BitReg<0, "dummy_lfh0_h">;
274+
def dummy_lfl0_l : AIE2P3BitReg<0, "dummy_lfl0_l">;
275+
def dummy_lfl0_h : AIE2P3BitReg<0, "dummy_lfl0_h">;
276+
277+
def dummy_lfh1_l : AIE2P3BitReg<0, "dummy_lfh1_l">;
278+
def dummy_lfh1_h : AIE2P3BitReg<0, "dummy_lfh1_h">;
279+
def dummy_lfl1_l : AIE2P3BitReg<0, "dummy_lfl1_l">;
280+
def dummy_lfl1_h : AIE2P3BitReg<0, "dummy_lfl1_h">;
281+
}
282+
283+
let SubRegIndices = [sub_256_lo, sub_256_hi], CoveredBySubRegs = 1 in {
265284
// Store FIFO register
266-
def sfh : AIE2P3BitReg<0b110,"sfh">;
267-
def sfl : AIE2P3BitReg<0b011,"sfl">;
285+
def sfh : AIE2P3BitReg<0b110,"sfh", [dummy_sfh_l, dummy_sfh_h]>;
286+
def sfl : AIE2P3BitReg<0b011,"sfl", [dummy_sfl_l, dummy_sfl_h]>;
268287
// Load FIFO register 0
269-
def lfh0 : AIE2P1BitReg<0b0,"lfh0">;
270-
def lfl0 : AIE2P1BitReg<0b0,"lfl0">;
288+
def lfh0 : AIE2P1BitReg<0b0,"lfh0", [dummy_lfh0_l, dummy_lfh0_h]>;
289+
def lfl0 : AIE2P1BitReg<0b0,"lfl0", [dummy_lfl0_l, dummy_lfl0_h]>;
271290
// Load FIFO register 1
272-
def lfh1 : AIE2P1BitReg<0b1,"lfh1">;
273-
def lfl1 : AIE2P1BitReg<0b1,"lfl1">;
291+
def lfh1 : AIE2P1BitReg<0b1,"lfh1", [dummy_lfh1_l, dummy_lfh1_h]>;
292+
def lfl1 : AIE2P1BitReg<0b1,"lfl1", [dummy_lfl1_l, dummy_lfl1_h]>;
293+
}
294+
274295
// Load FIFO extra register
275296
def lfe : AIE2P3BitReg<0b010,"lfe">;
276297

277298
def sub_lo_fifo: SubRegIndex<512, 0>;
278299
def sub_hi_fifo : SubRegIndex<512, 512>;
279-
let SubRegIndices = [sub_lo_fifo, sub_hi_fifo], CoveredBySubRegs = 1 in {
300+
let SubRegIndices = [sub_512_lo, sub_512_hi], CoveredBySubRegs = 1 in {
280301
def lf0 : AIE2P1BitReg<0b0, "lf0", [lfl0, lfh0]>;
281302
def lf1 : AIE2P1BitReg<0b1, "lf1", [lfl1, lfh1]>;
282303
def sf : AIE2P1BitReg<0b1, "sf", [sfl, sfh]>;
@@ -990,9 +1011,9 @@ def spill_eDN_to_eR : AIE2PScalarRegisterClass<(add eDN, eR)>;
9901011
def spill_eDJ_to_eR : AIE2PScalarRegisterClass<(add eDJ, eR, eDN)>;
9911012
def spill_eDC_to_eR : AIE2PScalarRegisterClass<(add eDC, eR)>;
9921013

993-
def spill_vec512_to_composite : AIE2PVector512RegisterClass<(add mXm, mBMm)>;
994-
def spill_vec1024_to_composite : AIE2PVector1024RegisterClass<(add eY, mCMm)>;
995-
def spill_acc512_to_composite : AIE2PVector512RegisterClass<(add mBMm, mXm)>;
996-
def spill_acc1024_to_composite : AIE2PVector1024RegisterClass<(add mCMm, eY)>;
1014+
def spill_vec512_to_composite : AIE2PVector512RegisterClass<(add mXm, mBMm, sfh, sfl, lfh0, lfh1, lfl0, lfl1)>;
1015+
def spill_vec1024_to_composite : AIE2PVector1024RegisterClass<(add eY, mCMm, lf0, lf1, sf)>;
1016+
def spill_acc512_to_composite : AIE2PVector512RegisterClass<(add mBMm, mXm, sfh, sfl, lfh0, lfh1, lfl0, lfl1)>;
1017+
def spill_acc1024_to_composite : AIE2PVector1024RegisterClass<(add mCMm, eY, lf0, lf1, sf)>;
9971018

9981019
} // End AIE2P Namespace

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