[AIE][WAWRewriter] Auto select latency/swpaware and swpaware bias

Author: Martien de Jong

llvm/lib/Target/AIE/AIEWawRegRewriter.cpp

@@ -116,27 +116,24 @@ RewriteMode selectMode(RewriteMode Mode, int LoopClass) {
   }
 }
 
-bool runSWPAware(RewriteMode Mode, int LoopClass, int &Bias) {
-  Bias = MinIIBias;
+std::optional<int> getMinIIBias(RewriteMode Mode, int LoopClass) {
   switch (Mode) {
   case RewriteMode::SWPAwareAutoBias:
     break;
   case RewriteMode::SWPAware:
-    return true;
+    return MinIIBias;
   default:
-    return false;
+    return {};
   }
 
   switch (LoopClass) {
   case 14:
-    Bias = -1;
-    return true;
+    return -1;
   case 18:
   case 29:
-    Bias = 1;
-    return true;
+    return 1;
   default:
-    return true;
+    return MinIIBias;
   }
 }
 
@@ -598,9 +595,8 @@ bool AIEWawRegRewriter::renameMBBPhysRegs(const MachineBasicBlock *MBB) {
     }
   }
 
-  int Bias = MinIIBias;
-  if (runSWPAware(Mode, LoopClass, Bias)) {
-    sortSWPAware(Candidates, NonConstMBB, Statistics, Bias);
+  if (auto Bias = getMinIIBias(Mode, LoopClass)) {
+    sortSWPAware(Candidates, NonConstMBB, Statistics, *Bias);
   }
 
   // Least-Recently-Used list of physical registers for assignments to VRegs.

llvm/test/CodeGen/AIE/aie2/end-to-end/TanhTemplated-swp.ll

@@ -7,7 +7,6 @@
 ; (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
 
 ; RUN: llc -O2 -mtriple=aie2 \
-; RUN:    --aie-reg-rewrite-mode=latencyaware \
 ; RUN:    %s -o - | FileCheck %s
 
 ; The test is meant as a quick way to spot QoR regressions. In this test, the
@@ -112,22 +111,22 @@ define dso_local void @TanhTemplated(ptr noalias %ifm, ptr noalias %ofm, ptr non
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    nopb ; nopa ; nops ; nopx ; vband x9, x10, x3; nopv
 ; CHECK-NEXT:    vldb wl7, [p0], #32; vmov wh3, wl2
-; CHECK-NEXT:    nopx ; vmov wh9, wl2; vmul.f bmh5, x7, x0, r1
-; CHECK-NEXT:    vconv.bf16.fp32 wl7, bml4; vldb wl7, [p0], #32; vmax_lt.bf16 x5, r16, x11, x8; vmac.f bmh4, bmh0, x3, x4, r1
+; CHECK-NEXT:    nopx ; vmov wh9, wl2; vmul.f bmh4, x7, x0, r1
+; CHECK-NEXT:    vconv.bf16.fp32 wl7, bml4; vldb wl7, [p0], #32; vmax_lt.bf16 x5, r16, x11, x8; vmac.f bmh3, bmh0, x3, x4, r1
 ; CHECK-NEXT:    vband x9, x10, x5; vmul.f bmh2, x6, x9, r1
-; CHECK-NEXT:    vmov wh9, wl2; vmul.f bmh6, x7, x0, r1
-; CHECK-NEXT:    vsub.f bml0, bmh5, bmh1, r0
-; CHECK-NEXT:    vmul.f bmh3, x6, x9, r1
-; CHECK-NEXT:    vmul.f bmh7, x0, x7, r1
-; CHECK-NEXT:    vmov wh5, wl2; vsub.f bml1, bmh6, bmh1, r0
+; CHECK-NEXT:    vmov wh9, wl2; vmul.f bmh5, x7, x0, r1
+; CHECK-NEXT:    vsub.f bml1, bmh4, bmh1, r0
+; CHECK-NEXT:    vmul.f bmh7, x6, x9, r1
+; CHECK-NEXT:    vmul.f bmh6, x0, x7, r1
+; CHECK-NEXT:    vmov wh5, wl2; vsub.f bml2, bmh5, bmh1, r0
 ; CHECK-NEXT:    vconv.bf16.fp32 wl7, bmh2; vmul.f bmh8, x0, x7, r1
-; CHECK-NEXT:    vmac.f bml2, bmh0, x5, x4, r1
-; CHECK-NEXT:    vmsc.f bml3, bmh4, x7, x3, r1
-; CHECK-NEXT:    vconv.bf16.fp32 wl3, bmh3
+; CHECK-NEXT:    vmac.f bml0, bmh0, x5, x4, r1
+; CHECK-NEXT:    vmsc.f bml3, bmh3, x7, x3, r1
 ; CHECK-NEXT:    vconv.bf16.fp32 wl3, bmh7
-; CHECK-NEXT:    vst.conv.bf16.fp32 bml0, [p1], #32; vmsc.f bml4, bml2, x3, x5, r1
+; CHECK-NEXT:    vconv.bf16.fp32 wl3, bmh6
+; CHECK-NEXT:    vst.conv.bf16.fp32 bml1, [p1], #32; vmsc.f bml4, bml0, x3, x5, r1
 ; CHECK-NEXT:    vconv.bf16.fp32 wl5, bmh8; vmin_ge.bf16 x9, r16, x3, x1
-; CHECK-NEXT:    vst.conv.bf16.fp32 bml1, [p1], #32; vmax_lt.bf16 x3, r16, x9, x8
+; CHECK-NEXT:    vst.conv.bf16.fp32 bml2, [p1], #32; vmax_lt.bf16 x3, r16, x9, x8
 ; CHECK-NEXT:  .L_LEnd0:
 ; CHECK-NEXT:    nopb ; nopa ; vconv.bf16.fp32 wl7, bml3; nopx ; vmin_ge.bf16 x11, r16, x5, x1; nopv
 ; CHECK-NEXT:  // %bb.2: