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Clean up
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+29
-5
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3 files changed

+29
-5
lines changed

mlir/include/mlir/Dialect/Linalg/Utils/Utils.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@
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#include "mlir/Dialect/Linalg/IR/Linalg.h"
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#include "mlir/Dialect/SCF/IR/SCF.h"
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#include "mlir/Dialect/Utils/StructuredOpsUtils.h"
15-
#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringSet.h"
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#include <optional>
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@@ -177,8 +176,7 @@ Operation *makeTiledShape(OpBuilder &builder, Location loc, Value valueToTile,
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ArrayRef<OpFoldResult> lbs,
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ArrayRef<OpFoldResult> ubs,
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ArrayRef<OpFoldResult> subShapeSizes,
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bool omitPartialTileCheck,
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ArrayRef<OpFoldResult> sizeBounds = {});
179+
bool omitPartialTileCheck);
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/// Creates extract_slice/subview ops for all `valuesToTile` of the given
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/// `linalgOp` with `builder`, assuming `linalgOp` is being fused into a loop

mlir/lib/Dialect/Linalg/Utils/Utils.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,6 @@ static bool isTiled(AffineExpr expr, ArrayRef<OpFoldResult> tileSizes,
9090
ArrayRef<int64_t> domainSizes) {
9191
if (!expr)
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return false;
93-
9493
TileCheck t(tileSizes, domainSizes);
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t.visit(expr);
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return t.isTiled;
@@ -612,7 +611,6 @@ SliceParameters computeSliceParameters(
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613612
// Tiling creates a new slice at the proper index, the slice step is 1
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// (i.e. the op does not subsample, stepping occurs in the loop).
615-
auto m = map.getSubMap({r});
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LLVM_DEBUG(llvm::dbgs() << "computeSliceParameters: submap: " << m << "\n");
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IRRewriter rewriter(builder);
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// The offset of the slice is map(lbs) - map(0).

mlir/test/Dialect/Linalg/tile-tensors.mlir

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -167,3 +167,31 @@ module attributes {transform.with_named_sequence} {
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transform.yield
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}
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}
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// -----
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func.func @non_monotonic_affine_expr(%arg0 : tensor<7xf32>) -> tensor<7xf32> {
174+
%c0 = arith.constant 0 : index
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%0 = tensor.dim %arg0, %c0 : tensor<7xf32>
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%empty = tensor.empty() : tensor<7xf32>
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// FIXME: Do proper testing
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// CHECK: tensor.extract_slice %arg2[0] [7] [1] : tensor<7xf32> to tensor<7xf32>
179+
%generic = linalg.generic
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{indexing_maps = [affine_map<(d0) -> (d0 mod 4)>,
181+
affine_map<(d0) -> (d0)>],
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iterator_types = ["parallel"]}
183+
ins(%arg0: tensor<7xf32>)
184+
outs(%empty : tensor<7xf32>) {
185+
^bb0(%in : f32, %out: f32):
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linalg.yield %in : f32
187+
} -> tensor<7xf32>
188+
return %generic : tensor<7xf32>
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}
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module attributes {transform.with_named_sequence} {
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transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) {
193+
%0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op
194+
%1, %loop = transform.structured.tile_using_for %0 tile_sizes [7] : (!transform.any_op) -> (!transform.any_op, !transform.any_op)
195+
transform.yield
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}
197+
}

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