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Enable lightweight instruction sequence compilation (#2643)
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3 files changed

+80
-34
lines changed

3 files changed

+80
-34
lines changed

python/compiler/aiecc/cl_arguments.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -101,14 +101,14 @@ def parse_args(args=None):
101101
dest="compile",
102102
default=not aie_disable_compile,
103103
action="store_true",
104-
help="Enable compiling of AIE code",
104+
help="Enable compiling of AIE code for each core in the array",
105105
)
106106
parser.add_argument(
107107
"--no-compile",
108108
dest="compile",
109109
default=not aie_disable_compile,
110110
action="store_false",
111-
help="Disable compiling of AIE code",
111+
help="Disable compiling of AIE code for each core in the array",
112112
)
113113
parser.add_argument(
114114
"--host-target",

python/compiler/aiecc/main.py

Lines changed: 53 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1460,45 +1460,66 @@ async def run_flow(self):
14601460
self.opts.verbose,
14611461
)
14621462

1463-
input_physical = self.prepend_tmp("input_physical.mlir")
1464-
processes = [
1465-
self.do_call(
1466-
task1,
1467-
[
1468-
"aie-opt",
1469-
"--aie-create-pathfinder-flows",
1470-
file_with_addresses,
1471-
"-o",
1472-
input_physical,
1473-
],
1474-
force=True,
1475-
)
1476-
]
1477-
1478-
await asyncio.gather(*processes)
1463+
requires_routing = (
1464+
opts.xcl
1465+
or opts.cdo
1466+
or opts.pdi
1467+
or opts.compile
1468+
or opts.compile_host
1469+
or opts.aiesim
1470+
)
1471+
if requires_routing:
1472+
input_physical = self.prepend_tmp("input_physical.mlir")
1473+
processes = [
1474+
self.do_call(
1475+
task1,
1476+
[
1477+
"aie-opt",
1478+
"--aie-create-pathfinder-flows",
1479+
file_with_addresses,
1480+
"-o",
1481+
input_physical,
1482+
],
1483+
force=True,
1484+
)
1485+
]
1486+
await asyncio.gather(*processes)
1487+
else:
1488+
input_physical = file_with_addresses
14791489

14801490
self.progress_bar.update(task1, advance=1)
14811491

14821492
# 2.) Generate code for each core
1483-
task2 = progress_bar.add_task(
1484-
"[green] Generating code for each core", total=3, command=""
1493+
requires_core_compilation = (
1494+
opts.xcl
1495+
or opts.cdo
1496+
or opts.pdi
1497+
or opts.compile
1498+
or opts.compile_host
1499+
or opts.aiesim
14851500
)
1501+
if requires_core_compilation:
1502+
task2 = progress_bar.add_task(
1503+
"[green] Generating code for each core", total=3, command=""
1504+
)
14861505

1487-
# create core ELF files for each device and core
1488-
elf_paths = {}
1489-
for i, (device_op, device_name) in enumerate(devices):
1490-
aie_target, aie_peano_target = aie_targets[i], aie_peano_targets[i]
1491-
elf_paths[device_name] = await self.process_cores(
1492-
device_op,
1493-
device_name,
1494-
file_with_addresses,
1495-
aie_target,
1496-
aie_peano_target,
1497-
task2,
1506+
# create core ELF files for each device and core
1507+
elf_paths = {}
1508+
for i, (device_op, device_name) in enumerate(devices):
1509+
aie_target, aie_peano_target = aie_targets[i], aie_peano_targets[i]
1510+
elf_paths[device_name] = await self.process_cores(
1511+
device_op,
1512+
device_name,
1513+
file_with_addresses,
1514+
aie_target,
1515+
aie_peano_target,
1516+
task2,
1517+
)
1518+
input_physical_with_elfs = await self.write_elf_paths_to_mlir(
1519+
input_physical, elf_paths
14981520
)
1499-
input_physical_with_elfs = await self.write_elf_paths_to_mlir(
1500-
input_physical, elf_paths
1501-
)
1521+
else:
1522+
input_physical_with_elfs = input_physical
15021523

15031524
# 3.) Targets that require the cores to be lowered but apply across all devices
15041525

test/aiecc/only_insts.mlir

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
//===- only_nsts.mlir ------------------------------------------*- MLIR -*-===//
2+
//
3+
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
// (c) Copyright 2025 Xilinx Inc.
8+
//
9+
//===----------------------------------------------------------------------===//
10+
11+
// Check that passing the --no-compile flag with --aie-generate-npu-insts generates _only_ the NPU instructions and skips other expensive compilation steps.
12+
13+
// RUN: %PYTHON aiecc.py -v --no-compile --aie-generate-npu-insts --npu-insts-name=my_insts.bin %s | FileCheck %s
14+
// RUN: ls | FileCheck %s --check-prefix=LS
15+
// CHECK-NOT: xchesscc_wrapper
16+
// LS: my_insts.bin
17+
18+
module {
19+
aie.device(npu2) {
20+
%12 = aie.tile(1, 2)
21+
aiex.runtime_sequence @seq(%buf : memref<1xi32>) {
22+
aiex.npu.sync { channel = 0 : i32, column = 0 : i32, column_num = 1 : i32, direction = 1 : i32, row = 0 : i32, row_num = 1 : i32 }
23+
}
24+
}
25+
}

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