Disable lowering arith.subf on 16-lane vectors to aievec.sub_elem (#2617)

Author: erwei-xilinx

lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp

@@ -3660,14 +3660,7 @@ static void configureAIEVecV2Legalizations(ConversionTarget &target,
     return laneSize != 16;
   });
 
-  target.addDynamicallyLegalOp<arith::SubFOp>([](arith::SubFOp op) {
-    auto resultType = dyn_cast<VectorType>(op.getType());
-    if (!resultType)
-      return true;
-
-    unsigned laneSize = getVectorLaneSize(resultType);
-    return laneSize != 16;
-  });
+  target.addLegalOp<arith::SubFOp>();
 
   target.addDynamicallyLegalOp<arith::MulIOp>([](arith::MulIOp op) {
     auto resultType = dyn_cast<VectorType>(op.getType());

test/Conversion/VectorToAIEVec/test-arith-aie2.mlir

@@ -188,30 +188,24 @@ func.func @vecaddf_bf16(%arg0: vector<16xbf16>, %arg1: vector<16xbf16>) -> vecto
   return %0 : vector<16xbf16>
 }
 
+// Use llvm-aie to lower arith.subf on vectors.
 // CHECK-LABEL: func @vecsubf_f32(
 // CHECK-SAME: %[[LHS:.*]]: vector<16xf32>,
 // CHECK-SAME: %[[RHS:.*]]: vector<16xf32>)
 func.func @vecsubf_f32(%arg0: vector<16xf32>, %arg1: vector<16xf32>) -> vector<16xf32> {
-  // CHECK:  %[[LCAST:.*]] = aievec.cast %[[LHS]] {isResAcc = true} : vector<16xf32>, vector<16xf32>
-  // CHECK:  %[[RCAST:.*]] = aievec.cast %[[RHS]] {isResAcc = true} : vector<16xf32>, vector<16xf32>
-  // CHECK:  %[[SUB:.*]] = aievec.sub_elem %[[LCAST]], %[[RCAST:.*]] : vector<16xf32>
-  // CHECK:  %[[CAST:.*]] = aievec.cast %[[SUB]] {isResAcc = false} : vector<16xf32>, vector<16xf32>
+  // CHECK:  %[[SUB:.*]] = arith.subf %[[LHS]], %[[RHS]] : vector<16xf32>
   %0 = arith.subf %arg0, %arg1 : vector<16xf32>
-  // CHECK: return %[[CAST]] : vector<16xf32>
+  // CHECK: return %[[SUB]] : vector<16xf32>
   return %0 : vector<16xf32>
 }
 
 // CHECK-LABEL: func @vecsubf_bf16(
 // CHECK-SAME: %[[LHS:.*]]: vector<16xbf16>,
 // CHECK-SAME: %[[RHS:.*]]: vector<16xbf16>)
 func.func @vecsubf_bf16(%arg0: vector<16xbf16>, %arg1: vector<16xbf16>) -> vector<16xbf16> {
-  // CHECK:  %[[C0:.*]] = arith.constant 0 : i32
-  // CHECK:  %[[LUPS:.*]] = aievec.ups %[[LHS]] {shift = 0 : i8} : vector<16xbf16>, vector<16xf32>
-  // CHECK:  %[[RUPS:.*]] = aievec.ups %[[RHS]] {shift = 0 : i8} : vector<16xbf16>, vector<16xf32>
-  // CHECK:  %[[SUB:.*]] = aievec.sub_elem %[[LUPS]], %[[RUPS]] : vector<16xf32>
-  // CHECK:  %[[SRS:.*]] = aievec.srs %[[SUB]], %[[C0]] : vector<16xf32>, i32, vector<16xbf16>
+  // CHECK:  %[[SUB:.*]] = arith.subf %[[LHS]], %[[RHS]] : vector<16xbf16>
   %0 = arith.subf %arg0, %arg1 : vector<16xbf16>
-  // CHECK: return %[[SRS]] : vector<16xbf16>
+  // CHECK: return %[[SUB]] : vector<16xbf16>
   return %0 : vector<16xbf16>
 }