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keryellkeryell
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[asm] Specialize tile SSA names according to the tile kind (#2025)
1 parent 2f6086e commit f1c3275

27 files changed

+466
-459
lines changed

‎.gitignore

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,5 @@ lib/**/Makefile
2525
/platforms/vck190_bare/vivado/vck190_bare_proj
2626
utils/vitisVariables.config
2727
runtime_lib/xaiengine/src
28+
/ironenv
29+
/.cache

‎include/aie/Dialect/AIE/IR/AIEOps.td

Lines changed: 28 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -130,9 +130,18 @@ def AIE_TileOp: AIE_Op<"tile", [
130130
let extraClassDefinition = [{
131131
void $cppClass::getAsmResultNames(
132132
function_ref<void(::mlir::Value, ::llvm::StringRef)> setNameFn) {
133-
std::string nameWithoutDialect =
133+
std::string tileName =
134134
getOperationName().str().substr(getOperationName().find('.') + 1);
135-
setNameFn(getResult(), nameWithoutDialect + "_" +
135+
// Specialize the SSA value name according to the tile kind
136+
if (isMemTile())
137+
tileName = "mem_" + tileName;
138+
else if (isShimNOCTile())
139+
tileName = "shim_noc_" + tileName;
140+
else if (isShimPLTile())
141+
tileName = "shim_pl_" + tileName;
142+
else if (isShimTile())
143+
tileName = "shim_" + tileName;
144+
setNameFn(getResult(), tileName + "_" +
136145
std::to_string(getCol()) + "_" +
137146
std::to_string(getRow()));
138147
}
@@ -642,13 +651,13 @@ def AIE_PacketFlowOp: AIE_Op<"packet_flow", [SingleBlockImplicitTerminator<"EndO
642651
let description = [{
643652
A logical packet-switched flow between tiles. During place and
644653
route, this is replaced by MasterSets and PacketRules inside
645-
switchboxes.
646-
647-
The optional attribute keep_pkt_header indicates whether each
648-
data packet's packet header gets preserved at the flow's
654+
switchboxes.
655+
656+
The optional attribute keep_pkt_header indicates whether each
657+
data packet's packet header gets preserved at the flow's
649658
destination. The optional attribute priority_route indicates
650-
whether the packet flow is routed in priority over other flows,
651-
so that they always get allocated with the same master, slave
659+
whether the packet flow is routed in priority over other flows,
660+
so that they always get allocated with the same master, slave
652661
ports, arbiters and master selects (msel).
653662

654663
Example:
@@ -864,9 +873,9 @@ def AIE_DMABDOp: AIE_Op<"dma_bd", []> {
864873
## DMA constant padding on AIE-ML Devices
865874

866875
AIE-ML devices can apply constant padding at the buffer descriptor level, described with pairs of padding
867-
counts before and after a dimension, to all dimensions in the data layout transformations. The padding
868-
counts can be supplied to the `dma_bd` through an optional argument, an array of "tuple-like" attributes
869-
`bd_pad_layout<const_pad_before, const_pad_after>`, followed by an optional argument `const_val` (default
876+
counts before and after a dimension, to all dimensions in the data layout transformations. The padding
877+
counts can be supplied to the `dma_bd` through an optional argument, an array of "tuple-like" attributes
878+
`bd_pad_layout<const_pad_before, const_pad_after>`, followed by an optional argument `const_val` (default
870879
is 0). All counts are expressed in multiples of the element width.
871880
}];
872881

@@ -1004,7 +1013,7 @@ def AIE_DMAStartOp: AIE_Op<"dma_start", [
10041013
bool isSend() { return getChannelDir() == DMAChannelDir::MM2S; }
10051014
bool isRecv() { return getChannelDir() == DMAChannelDir::S2MM; }
10061015
}];
1007-
1016+
10081017
let hasCanonicalizer = 1;
10091018
}
10101019

@@ -1467,8 +1476,8 @@ def AIE_CascadeFlowOp: AIE_Op<"cascade_flow", []> {
14671476
);
14681477
let summary = "A cascade connection between tiles";
14691478
let description = [{
1470-
The `aie.cascade_flow` operation represents a cascade connection between two `aie.tile` operations.
1471-
During lowering, this is replaced by `aie.configure_cascade` operations for each `aie.tile` based on
1479+
The `aie.cascade_flow` operation represents a cascade connection between two `aie.tile` operations.
1480+
During lowering, this is replaced by `aie.configure_cascade` operations for each `aie.tile` based on
14721481
their relative placement to one another.
14731482

14741483
Example:
@@ -1491,7 +1500,7 @@ def AIE_CascadeFlowOp: AIE_Op<"cascade_flow", []> {
14911500
def AIE_ConfigureCascadeOp: AIE_Op<"configure_cascade", [HasParent<"DeviceOp">]> {
14921501
let summary = "An op to configure the input and output directions of the cascade for a single AIE tile";
14931502
let description = [{
1494-
An operation to configure the cascade on a single tile in both the input and the output
1503+
An operation to configure the cascade on a single tile in both the input and the output
14951504
directions.
14961505

14971506
Example:
@@ -1666,7 +1675,7 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [HasParent<"DeviceOp">, Symbol]
16661675
BDDimLayoutArrayArrayAttr:$dimensionsFromStreamPerConsumer,
16671676
DefaultValuedAttr<BoolAttr, "false">:$via_DMA,
16681677
DefaultValuedAttr<BoolAttr, "false">:$plio,
1669-
// disable_synchronization==true will skip lock generation for
1678+
// disable_synchronization==true will skip lock generation for
16701679
// objectfifo synchronous accesses
16711680
DefaultValuedAttr<BoolAttr, "false">:$disable_synchronization,
16721681
// via_shared_mem==0 means use producer tile's memory module
@@ -1915,7 +1924,7 @@ def AIE_ObjectFifoSubviewAccessOp : AIE_Op<"objectfifo.subview.access", []> {
19151924
}];
19161925

19171926
let arguments = (
1918-
ins AIE_ObjectFifoSubviewType:$subview,
1927+
ins AIE_ObjectFifoSubviewType:$subview,
19191928
ConfinedAttr<AIEI32Attr, [IntMinValue<0>]>:$index
19201929
);
19211930

@@ -2007,11 +2016,11 @@ def AIE_ObjectFifoRegisterProcessOp: AIE_Op<"objectfifo.register_process", []> {
20072016
def AIE_BDChainOp: AIE_Op<"bd_chain", [Symbol, SkipAccessibilityCheckTrait]> {
20082017
let summary = "Definition of a Parametrizable Chain of Buffer Descriptors";
20092018
let description = [{
2010-
This operation allows you to define buffer descriptor chains with parametrizable inputs.
2019+
This operation allows you to define buffer descriptor chains with parametrizable inputs.
20112020
This is useful for common patterns such as double buffering (ping-pong) that may look identical but use different input/output buffers and locks.
20122021
Currently, only buffers and locks are parametrizable.
20132022

2014-
Once defined, an abstract BD chain can be used elsewhere using AIEX ops in the runtime sequence.
2023+
Once defined, an abstract BD chain can be used elsewhere using AIEX ops in the runtime sequence.
20152024
In the future, abstract BD chains will also be usable elsewhere, inside the static configuration.
20162025
At its usage sites, the abstract BD chain will be concretized with the given input arguments.
20172026
}];

‎test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
//===----------------------------------------------------------------------===//
1010

1111
// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s
12-
// CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16384xi32>
12+
// CHECK: %a = aie.buffer(%{{.*}}_3_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16384xi32>
1313

1414
module @test {
1515
aie.device(xcve2302) {

‎test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,9 @@
1111
// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s
1212
// CHECK: module @test {
1313
// CHECK: aie.device(xcve2302) {
14-
// CHECK: %tile_3_1 = aie.tile(3, 1)
15-
// CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, sym_name = "a"} : memref<65536xi32>
16-
// CHECK: %memtile_dma_3_1 = aie.memtile_dma(%tile_3_1) {
14+
// CHECK: %mem_tile_3_1 = aie.tile(3, 1)
15+
// CHECK: %a = aie.buffer(%mem_tile_3_1) {address = 0 : i32, sym_name = "a"} : memref<65536xi32>
16+
// CHECK: %memtile_dma_3_1 = aie.memtile_dma(%mem_tile_3_1) {
1717
// CHECK: aie.end
1818
// CHECK: }
1919
// CHECK: }

‎test/bd-chains-and-dma-tasks/assign-runtime-sequence-bd-ids/good-1.mlir

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,9 @@ module {
2626
}
2727

2828
aiex.runtime_sequence(%arg0: memref<8xi16>, %arg1: memref<12xi16>, %arg2: memref<8xi16>) {
29-
%t1 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg2) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
30-
on (%tile_0_0, MM2S, 0)
31-
// CHECK: %[[task1:.+]] = aiex.dma_configure_task(%tile_0_0, MM2S, 0) {
29+
%t1 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg2) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
30+
on (%tile_0_0, MM2S, 0)
31+
// CHECK: %[[task1:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, MM2S, 0) {
3232
// CHECK: aie.dma_bd(%arg0 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>]) {bd_id = 0 : i32}
3333
// CHECK: aie.next_bd ^bb1
3434
// CHECK: ^bb1:
@@ -39,9 +39,9 @@ module {
3939
// CHECK: aie.end
4040
// CHECK: }
4141
// CHECK: aiex.dma_start_task(%[[task1]])
42-
%t2 = aiex.dma_start_bd_chain @simple_chain(%arg2, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
43-
on (%tile_0_0, MM2S, 1)
44-
// CHECK: %[[task2:.+]] = aiex.dma_configure_task(%tile_0_0, MM2S, 1) {
42+
%t2 = aiex.dma_start_bd_chain @simple_chain(%arg2, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
43+
on (%tile_0_0, MM2S, 1)
44+
// CHECK: %[[task2:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, MM2S, 1) {
4545
// CHECK: aie.dma_bd(%arg2 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>]) {bd_id = 3 : i32}
4646
// CHECK: aie.next_bd ^bb1
4747
// CHECK: ^bb1:
@@ -52,9 +52,9 @@ module {
5252
// CHECK: aie.end
5353
// CHECK: }
5454
// CHECK: aiex.dma_start_task(%[[task2]])
55-
%t3 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
56-
on (%tile_0_0, S2MM, 0)
57-
// CHECK: %[[task3:.+]] = aiex.dma_configure_task(%tile_0_0, S2MM, 0) {
55+
%t3 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
56+
on (%tile_0_0, S2MM, 0)
57+
// CHECK: %[[task3:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, S2MM, 0) {
5858
// CHECK: aie.dma_bd(%arg0 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>]) {bd_id = 6 : i32}
5959
// CHECK: aie.next_bd ^bb1
6060
// CHECK: ^bb1:
@@ -69,4 +69,3 @@ module {
6969
}
7070
}
7171
}
72-

‎test/bd-chains-and-dma-tasks/dma-tasks-to-npu/good-5.mlir

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,10 @@ module {
1717
%tile_0_0 = aie.tile(0, 0)
1818
%tile_0_1 = aie.tile(0, 1)
1919
%tile_0_2 = aie.tile(0, 2)
20-
// CHECK: %{{.*}} = aie.buffer(%tile_0_1) {address = [[ADDR1:[0-9]+]] {{.*}}}
21-
%buf0 = aie.buffer(%tile_0_1) : memref<32xi8>
22-
// CHECK: %{{.*}} = aie.buffer(%tile_0_1) {address = [[ADDR2:[0-9]+]] {{.*}}}
23-
%buf1 = aie.buffer(%tile_0_1) : memref<32xi8>
20+
// CHECK: %{{.*}} = aie.buffer(%{{.*}}tile_0_1) {address = [[ADDR1:[0-9]+]] {{.*}}}
21+
%buf0 = aie.buffer(%tile_0_1) : memref<32xi8>
22+
// CHECK: %{{.*}} = aie.buffer(%{{.*}}tile_0_1) {address = [[ADDR2:[0-9]+]] {{.*}}}
23+
%buf1 = aie.buffer(%tile_0_1) : memref<32xi8>
2424

2525
aiex.runtime_sequence(%arg0: memref<32xi8>) {
2626
%t1 = aiex.dma_configure_task(%tile_0_1, MM2S, 0) {
@@ -35,4 +35,3 @@ module {
3535
}
3636
}
3737
}
38-

‎test/bd-chains-and-dma-tasks/materialize-bd-chains/good-1.mlir

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
// RUN: aie-opt --aie-materialize-bd-chains %s | FileCheck %s
99

1010
// This test ensures that a BD chains get lowered to correct `aiex.dma_configure_task`
11-
// operations at their usage sites. We particularly ensure that the input arguments
11+
// operations at their usage sites. We particularly ensure that the input arguments
1212
// are correctly substituted.
1313

1414
module {
@@ -28,9 +28,9 @@ module {
2828
}
2929

3030
aiex.runtime_sequence(%arg0: memref<8xi16>, %arg1: memref<12xi16>, %arg2: memref<8xi16>) {
31-
%t1 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg2) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
32-
on (%tile_0_0, MM2S, 0)
33-
// CHECK: %[[task1:.+]] = aiex.dma_configure_task(%tile_0_0, MM2S, 0) {
31+
%t1 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg2) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
32+
on (%tile_0_0, MM2S, 0)
33+
// CHECK: %[[task1:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, MM2S, 0) {
3434
// CHECK: aie.dma_bd(%arg0 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>])
3535
// CHECK: aie.next_bd ^bb1
3636
// CHECK: ^bb1:
@@ -41,9 +41,9 @@ module {
4141
// CHECK: aie.end
4242
// CHECK: }
4343
// CHECK: aiex.dma_start_task(%[[task1]])
44-
%t2 = aiex.dma_start_bd_chain @simple_chain(%arg2, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
45-
on (%tile_0_0, MM2S, 1)
46-
// CHECK: %[[task2:.+]] = aiex.dma_configure_task(%tile_0_0, MM2S, 1) {
44+
%t2 = aiex.dma_start_bd_chain @simple_chain(%arg2, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
45+
on (%tile_0_0, MM2S, 1)
46+
// CHECK: %[[task2:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, MM2S, 1) {
4747
// CHECK: aie.dma_bd(%arg2 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>])
4848
// CHECK: aie.next_bd ^bb1
4949
// CHECK: ^bb1:
@@ -54,9 +54,9 @@ module {
5454
// CHECK: aie.end
5555
// CHECK: }
5656
// CHECK: aiex.dma_start_task(%[[task2]])
57-
%t3 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
58-
on (%tile_0_0, S2MM, 0)
59-
// CHECK: %[[task3:.+]] = aiex.dma_configure_task(%tile_0_0, S2MM, 0) {
57+
%t3 = aiex.dma_start_bd_chain @simple_chain(%arg0, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
58+
on (%tile_0_0, S2MM, 0)
59+
// CHECK: %[[task3:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, S2MM, 0) {
6060
// CHECK: aie.dma_bd(%arg0 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>])
6161
// CHECK: aie.next_bd ^bb1
6262
// CHECK: ^bb1:
@@ -71,4 +71,3 @@ module {
7171
}
7272
}
7373
}
74-

‎test/bd-chains-and-dma-tasks/materialize-bd-chains/good-5.mlir

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,9 @@ module {
2626
}
2727

2828
aiex.runtime_sequence(%arg0: memref<8xi16>, %arg1: memref<12xi16>, %arg2: memref<8xi16>) {
29-
%t1 = aiex.dma_start_bd_chain_for @simple_chain(%arg0, %arg1, %arg2) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
29+
%t1 = aiex.dma_start_bd_chain_for @simple_chain(%arg0, %arg1, %arg2) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
3030
for @alloc0
31-
// CHECK: %[[task1:.+]] = aiex.dma_configure_task(%tile_0_0, MM2S, 0) {
31+
// CHECK: %[[task1:.+]] = aiex.dma_configure_task(%{{.*}}tile_0_0, MM2S, 0) {
3232
// CHECK: aie.dma_bd(%arg0 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>])
3333
// CHECK: aie.next_bd ^bb1
3434
// CHECK: ^bb1:
@@ -39,9 +39,9 @@ module {
3939
// CHECK: aie.end
4040
// CHECK: }
4141
// CHECK: aiex.dma_start_task(%[[task1]])
42-
%t2 = aiex.dma_start_bd_chain_for @simple_chain(%arg2, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
42+
%t2 = aiex.dma_start_bd_chain_for @simple_chain(%arg2, %arg1, %arg0) : (memref<8xi16>, memref<12xi16>, memref<8xi16>)
4343
for @alloc1
44-
// CHECK: %[[task2:.+]] = aiex.dma_configure_task(%tile_2_0, MM2S, 1) {
44+
// CHECK: %[[task2:.+]] = aiex.dma_configure_task(%{{.*}}tile_2_0, MM2S, 1) {
4545
// CHECK: aie.dma_bd(%arg2 : memref<8xi16>, 0, 8, [<size = 1, stride = 0>, <size = 2, stride = 2>, <size = 2, stride = 4>, <size = 2, stride = 1>])
4646
// CHECK: aie.next_bd ^bb1
4747
// CHECK: ^bb1:
@@ -56,4 +56,3 @@ module {
5656
}
5757
}
5858
}
59-

‎test/create-flows/fixed_connections.mlir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,23 +10,23 @@
1010

1111
// RUN: aie-opt --aie-create-pathfinder-flows --split-input-file %s | FileCheck %s
1212

13-
// CHECK: %tile_2_0 = aie.tile(2, 0)
14-
// CHECK: %tile_3_0 = aie.tile(3, 0)
15-
// CHECK: %tile_6_0 = aie.tile(6, 0)
16-
// CHECK: %tile_7_0 = aie.tile(7, 0)
17-
// CHECK: %switchbox_2_0 = aie.switchbox(%tile_2_0) {
13+
// CHECK: %{{.*}}tile_2_0 = aie.tile(2, 0)
14+
// CHECK: %{{.*}}tile_3_0 = aie.tile(3, 0)
15+
// CHECK: %{{.*}}tile_6_0 = aie.tile(6, 0)
16+
// CHECK: %{{.*}}tile_7_0 = aie.tile(7, 0)
17+
// CHECK: %switchbox_2_0 = aie.switchbox(%{{.*}}tile_2_0) {
1818
// CHECK: aie.connect<North : 0, South : 2>
1919
// CHECK: aie.connect<North : 1, South : 3>
2020
// CHECK: }
21-
// CHECK: %switchbox_3_0 = aie.switchbox(%tile_3_0) {
21+
// CHECK: %switchbox_3_0 = aie.switchbox(%{{.*}}tile_3_0) {
2222
// CHECK: aie.connect<North : 0, South : 2>
2323
// CHECK: aie.connect<North : 1, South : 3>
2424
// CHECK: }
25-
// CHECK: %switchbox_6_0 = aie.switchbox(%tile_6_0) {
25+
// CHECK: %switchbox_6_0 = aie.switchbox(%{{.*}}tile_6_0) {
2626
// CHECK: aie.connect<North : 0, South : 2>
2727
// CHECK: aie.connect<North : 1, South : 3>
2828
// CHECK: }
29-
// CHECK: %switchbox_7_0 = aie.switchbox(%tile_7_0) {
29+
// CHECK: %switchbox_7_0 = aie.switchbox(%{{.*}}tile_7_0) {
3030
// CHECK: aie.connect<North : 0, South : 2>
3131
// CHECK: aie.connect<North : 1, South : 3>
3232
// CHECK: }

‎test/find-flows/shim.mlir

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -44,30 +44,30 @@ module {
4444

4545
// -----
4646

47-
// CHECK: %tile_2_1 = aie.tile(2, 1)
48-
// CHECK: %tile_2_0 = aie.tile(2, 0)
47+
// CHECK: %{{.*}}tile_2_1 = aie.tile(2, 1)
48+
// CHECK: %{{.*}}tile_2_0 = aie.tile(2, 0)
4949
// CHECK: %core_2_1 = aie.core(%tile_2_1) {
5050
// CHECK: aie.end
5151
// CHECK: }
52-
// CHECK: %switchbox_2_1 = aie.switchbox(%tile_2_1) {
52+
// CHECK: %switchbox_2_1 = aie.switchbox(%{{.*}}tile_2_1) {
5353
// CHECK: aie.connect<Core : 0, South : 0>
5454
// CHECK: }
55-
// CHECK: %switchbox_2_0 = aie.switchbox(%tile_2_0) {
55+
// CHECK: %switchbox_2_0 = aie.switchbox(%{{.*}}tile_2_0) {
5656
// CHECK: aie.connect<North : 0, South : 2>
5757
// CHECK: }
58-
// CHECK: %shim_mux_2_0 = aie.shim_mux(%tile_2_0) {
58+
// CHECK: %shim_mux_2_0 = aie.shim_mux(%{{.*}}tile_2_0) {
5959
// CHECK: aie.connect<North : 2, DMA : 0>
6060
// CHECK: }
61-
// CHECK: %shim_dma_2_0 = aie.shim_dma(%tile_2_0) {
61+
// CHECK: %shim_dma_2_0 = aie.shim_dma(%{{.*}}tile_2_0) {
6262
// CHECK: aie.end
6363
// CHECK: }
6464
// CHECK: aie.wire(%switchbox_2_1 : South, %switchbox_2_0 : North)
6565
// CHECK: aie.wire(%switchbox_2_0 : South, %shim_mux_2_0 : North)
6666
// CHECK: aie.wire(%shim_mux_2_0 : DMA, %shim_dma_2_0 : DMA)
67-
// CHECK: aie.wire(%shim_mux_2_0 : South, %tile_2_0 : DMA)
67+
// CHECK: aie.wire(%shim_mux_2_0 : South, %{{.*}}tile_2_0 : DMA)
6868
// CHECK: aie.wire(%switchbox_2_1 : Core, %core_2_1 : Core)
69-
// CHECK: aie.wire(%switchbox_2_1 : Core, %tile_2_1 : Core)
70-
// CHECK: aie.flow(%tile_2_1, Core : 0, %shim_dma_2_0, DMA : 0)
69+
// CHECK: aie.wire(%switchbox_2_1 : Core, %{{.*}}tile_2_1 : Core)
70+
// CHECK: aie.flow(%{{.*}}tile_2_1, Core : 0, %shim_dma_2_0, DMA : 0)
7171

7272
module {
7373
aie.device(xcvc1902) {
@@ -95,4 +95,4 @@ module {
9595
aie.wire(%s21 : Core, %c21 : Core)
9696
aie.wire(%s21 : Core, %t21 : Core)
9797
}
98-
}
98+
}

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