Writing from Compute Tile to Memory Tile at Different Offsets

[kurtis-b]

Does anyone know if there's a way to write from compute tile to memory tile at different offsets?

For example, if I have a core that generates a 64x64 matrix, save the data to memory tile that has a 64x256 buffer, run the core 3 more times, and save the subsequent outputs to fill up the 64x256 buffer in memory tile, is it possible?

I know it's possible if I have 4 compute tiles that each send 64x64 data to memory tile, but I'm not sure if it's possible with just 1 compute tile.

It seems like it might be possible at the buffer descriptor level since the offset can be set, but is there an example for it, or can anyone confirm? And is it possible at the objectFifo level?

[AndraBisca]

Hello @kurtis-b! This is indeed an interesting pattern. At the objectfifo level you could do this with a link: have one objectfifo of0 going from the compute tile to the memory tile with object size 64x64, and a second objectfifo of1 forwarded from the memory tile to the shim tile (or to some other tile) with object size 64x256. The DMAs will fill the 64x256 objects on the memory tile sequentially with the 64x64 tensors. Here is an example where you can see that the object size of of_out0 is three times that of of_out1.

One thing to observe here is that if no dimensions are given to the objectfifos, the 64x256 objects will be filled sequentially. If this is different than the layout you expect, you can write either dims_to_stream for of1 or default_dims_from_stream_per_cons for of0, or alternatively reshape your output in the host code.

[kurtis-b]

Thanks for the response! This is exactly what I was looking for.

I was also thinking about a case where the 64x256 object in memory tile that's filled sequentially by the (first) compute tile is used by another (second) compute tile, but only a subset of the data at a time, e.g. some operation using 64x32 of the 64x256 data in memory tile sequentially.

But I'm realizing if the second compute tile uses a subset of the first compute tile's output then it's probably better to try L1 fusion. And if the second compute tile needs the full 64x256 data generated by the first compute tile, then it seems better to implement the kind of pattern shown in the example you linked.