How to handle buffer descriptor exhaustion for complex tiling patterns

[dimdano]

Hi all,

We are developing AIE-ML kernels in Vitis (ADF graph, C++) targeting Versal devices and using adf::tiling for multi-dimensional data movement through memory tiles. For higher-dimensional buffers (e.g., 3D/4D) and complex tiling/traversal patterns, we frequently hit the compiler error: "Failed to allocate buffer descriptors due to insufficient number of available buffer descriptors."

It seems that a single tiling expression expands into more DMA transfers than the available BD slots per memory tile. What is the recommended approach when a tiling exceeds BD capacity? Does ADF/Vitis support BD reconfiguration in any form, and if yes, is this accessible at graph C++ level and how.

Any guidance or examples would be greatly appreciated.

Thanks!