diff --git a/include/aie/Dialect/AIEVec/AIE1/IR/AIEVecAIE1Ops.td b/include/aie/Dialect/AIEVec/AIE1/IR/AIEVecAIE1Ops.td
index 70c7f1f7755..b74346f24bc 100644
--- a/include/aie/Dialect/AIEVec/AIE1/IR/AIEVecAIE1Ops.td
+++ b/include/aie/Dialect/AIEVec/AIE1/IR/AIEVecAIE1Ops.td
@@ -36,7 +36,7 @@ def AIEVecAIE1_AddOp:
   AIEVecAIE1_Op<"add", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
                DefaultValuedStrAttr<StrAttr, "">:$xstart,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets_hi,
@@ -45,7 +45,7 @@ def AIEVecAIE1_AddOp:
                DefaultValuedStrAttr<StrAttr, "">:$zoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$zoffsets_hi,
                DefaultValuedStrAttr<StrAttr, "">:$zsquare)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE1 vector add";
   let description = [{
     AMD-specific advanced add operation that adds two 1-D vectors 
@@ -78,7 +78,7 @@ def AIEVecAIE1_SubOp:
   AIEVecAIE1_Op<"sub", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
                DefaultValuedStrAttr<StrAttr, "">:$xstart,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets_hi,
@@ -87,7 +87,7 @@ def AIEVecAIE1_SubOp:
                DefaultValuedStrAttr<StrAttr, "">:$zoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$zoffsets_hi,
                DefaultValuedStrAttr<StrAttr, "">:$zsquare)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE1 vector subtract";
   let description = [{
     AMD-specific advanced sub operation that subtracts two 1-D vectors
@@ -120,7 +120,7 @@ def AIEVecAIE1_MulOp:
   AIEVecAIE1_Op<"mul", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
                DefaultValuedStrAttr<StrAttr, "">:$xstart,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets_hi,
@@ -131,7 +131,7 @@ def AIEVecAIE1_MulOp:
                DefaultValuedStrAttr<StrAttr, "">:$zoffsets_hi,
                DefaultValuedStrAttr<StrAttr, "">:$zstep,
                DefaultValuedStrAttr<StrAttr, "">:$zsquare)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector multiply";
   let description = [{
     AMD-specific multiply operation that multiplies two 1-D vectors.
@@ -184,7 +184,8 @@ def AIEVecAIE1_FMAOp :
   AIEVecAIE1_Op<"mac", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, AnyVector:$acc,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
+               AnyVectorOfNonZeroRank:$acc,
                DefaultValuedStrAttr<StrAttr, "">:$xstart,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets_hi,
@@ -196,7 +197,7 @@ def AIEVecAIE1_FMAOp :
                DefaultValuedStrAttr<StrAttr, "">:$zstep,
                DefaultValuedStrAttr<StrAttr, "">:$zsquare,
                DefaultValuedAttr<BoolAttr, "false">:$fmsub)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector fused multiply-add";
   let description = [{
     AMD-specific multiply-add operation. It multiplies two 1-D vectors,
@@ -255,7 +256,7 @@ def AIEVecAIE1_SelectOp:
   AIEVecAIE1_Op<"select", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$xbuff,
+  Arguments<(ins AnyVectorOfNonZeroRank:$xbuff,
                DefaultValuedStrAttr<StrAttr, "">:$select,
                DefaultValuedStrAttr<StrAttr, "">:$xstart,
                DefaultValuedStrAttr<StrAttr, "">:$xoffsets,
@@ -265,8 +266,8 @@ def AIEVecAIE1_SelectOp:
                DefaultValuedStrAttr<StrAttr, "">:$yoffsets,
                DefaultValuedStrAttr<StrAttr, "">:$yoffsets_hi,
                DefaultValuedStrAttr<StrAttr, "">:$ysquare,
-               Optional<AnyVector>:$ybuff)>,
-  Results<(outs AnyVector:$result)> {
+               Optional<AnyVectorOfNonZeroRank>:$ybuff)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector lane selection";
   let description = [{
     AMD-specific vector lane selection operation. It selects between the
@@ -313,9 +314,9 @@ def AIEVecAIE1_ExtOp:
   AIEVecAIE1_Op<"ext", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$source,
+  Arguments<(ins AnyVectorOfNonZeroRank:$source,
              ConfinedAttr<AIEI8Attr, [IntMinValue<0>, IntMaxValue<8>]>:$index)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE ext";
   let description = [{
     AMD-specific vector extract intrinsic. Selects contiguous lanes from 
diff --git a/include/aie/Dialect/AIEVec/IR/AIEVecOps.td b/include/aie/Dialect/AIEVec/IR/AIEVecOps.td
index 39fe18c67d2..f78cecafc6a 100644
--- a/include/aie/Dialect/AIEVec/IR/AIEVecOps.td
+++ b/include/aie/Dialect/AIEVec/IR/AIEVecOps.td
@@ -40,8 +40,8 @@ def AIEVec_AddElemOp:
     Pure,
     AllTypesMatch<["lhs", "rhs", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector add elem";
   let description = [{
     AMD-specific AIE2 intrinsic that allows you to perform addition operation
@@ -57,8 +57,8 @@ def AIEVec_SubElemOp:
     Pure,
     AllTypesMatch<["lhs", "rhs", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector sub elem";
   let description = [{
     AMD-specific AIE2 intrinsic that allows you to perform substraction operation
@@ -73,9 +73,10 @@ def AIEVec_FMAElemOp :
   AIEVec_Op<"mac_elem", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, AnyVector:$acc,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
+               AnyVectorOfNonZeroRank:$acc,
                DefaultValuedAttr<BoolAttr, "false">:$fmsub)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 element-wise vector fused multiply-add";
   let description = [{
     AMD-specific multiply-add operation. It multiplies two 1-D vectors in the same channel,
@@ -130,9 +131,9 @@ def AIEVec_BroadcastOp:
   AIEVec_Op<"broadcast", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$source,
+  Arguments<(ins AnyVectorOfNonZeroRank:$source,
           DefaultValuedAttr<ConfinedAttr<AIEI8Attr, [IntNonNegative]>, "0">:$idx)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 broadcast";
   let description = [{
     AMD-specific broadcast intrinsic. Extract element index from vector and broadcasts its
@@ -150,7 +151,7 @@ def AIEVec_BroadcastScalarOp:
     Pure
   ]>,
   Arguments<(ins AnyTypeOf<[BF16, F32, I32, I16, I8]>:$source)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 broadcast scalar";
   let description = [{
     AMD-specific broadcast scalar intrinsic. Broadcasts input value to all vector lanes.
@@ -166,9 +167,9 @@ def AIEVec_UPSOp:
   AIEVec_Op<"ups", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$source,
+  Arguments<(ins AnyVectorOfNonZeroRank:$source,
           DefaultValuedAttr<ConfinedAttr<AIEI8Attr, [IntNonNegative]>, "0">:$shift)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE ups";
   let description = [{
     AMD-specific upshift intrinsic. Moves data from AIE vector data type
@@ -187,8 +188,9 @@ def AIEVec_CastOp:
   AIEVec_Op<"cast", [
     Pure
   ]>, 
-  Arguments<(ins AnyVector:$source, DefaultValuedAttr<BoolAttr, "false">:$isResAcc)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$source,
+             DefaultValuedAttr<BoolAttr, "false">:$isResAcc)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE cast";
   let description = [{
     AIE2 cast intrinsic. Cast values from source data type to result data types.
@@ -205,8 +207,8 @@ def AIEVec_SRSOp:
   AIEVec_Op<"srs", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$source, AnyInteger:$shift)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$source, AnyInteger:$shift)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE srs";
   let description = [{
     AMD-specific shift-round-saturate intrinsic. Moves values from
@@ -227,8 +229,8 @@ def AIEVec_UPDOp:
                  DefaultValuedAttr<AIEI32Attr, "0">:$offset,
                  DefaultValuedAttr<ConfinedAttr<AIEI8Attr,
                         [IntMinValue<0>, IntMaxValue<1>]>, "0">:$index,
-                 Optional<AnyVector>:$vector)>, 
-  Results<(outs AnyVector:$result)> {
+                 Optional<AnyVectorOfNonZeroRank>:$vector)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE upd";
   let description = [{
     AMD-specific update intrinsic. General upd intrinsic updates contiguous
@@ -250,8 +252,8 @@ def AIEVec_ConcatOp:
   AIEVec_Op<"concat", [
     Pure, InferTypeOpAdaptor,
   ]>, 
-  Arguments<(ins Variadic<AnyVector>:$sources)>, 
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins Variadic<AnyVectorOfNonZeroRank>:$sources)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE concat";
   let description = [{
     AMD-specific concat intrinsic. Concatenates two or more smaller
@@ -265,9 +267,9 @@ def AIEVec_ExtOp:
   AIEVec_Op<"ext", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$source,
+  Arguments<(ins AnyVectorOfNonZeroRank:$source,
              ConfinedAttr<AIEI8Attr, [IntMinValue<0>, IntMaxValue<8>]>:$index)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE ext";
   let description = [{
     AMD-specific vector extract intrinsic. Selects contiguous lanes from 
@@ -285,8 +287,8 @@ def AIEVec_PackOp:
   AIEVec_Op<"pack", [
     Pure
   ]>, 
-  Arguments<(ins AnyVector:$source)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$source)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE pack";
   let description = [{
     AMD-specific pack intrinsic. Pack a vector of 16-bit values into
@@ -299,8 +301,8 @@ def AIEVec_UnpackOp:
   AIEVec_Op<"unpack", [
     Pure
   ]>, 
-  Arguments<(ins AnyVector:$source)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$source)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE unpack";
   let description = [{
     AMD-specific unpack intrinsic. Unpack a vector of 8-bit values into
@@ -313,8 +315,9 @@ def AIEVec_ShiftOp:
   AIEVec_Op<"shift", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, I32:$shift, DefaultValuedAttr<BoolAttr, "false">:$isAcc)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
+             I32:$shift, DefaultValuedAttr<BoolAttr, "false">:$isAcc)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 concat and shift";
   let description = [{
     AMD-specific shift intrinsic. Concatenates two
@@ -330,9 +333,9 @@ def AIEVec_LegacyShuffleOp:
   AIEVec_Op<"legacyshuffle", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$source,
+  Arguments<(ins AnyVectorOfNonZeroRank:$source,
              DefaultValuedAttr<AIEI32Attr, "0">:$mode)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 shuffle";
   let description = [{
     AMD-specific vector shuffle intrinsic by a specific shuffle mode.
@@ -344,10 +347,10 @@ def AIEVec_MulConvOp:
   AIEVec_Op<"mul_conv", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
              DefaultValuedAttr<AIEI32Attr, "0">:$M,
              DefaultValuedAttr<AIEI32Attr, "0">:$N)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 multiply convolution";
   let description = [{
     AMD-specific multiply convolution intrinsic. Multiply convolution operation
@@ -365,11 +368,12 @@ def AIEVec_FMAConvOp:
   AIEVec_Op<"fma_conv", [
     Pure
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, AnyVector:$acc,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
+             AnyVectorOfNonZeroRank:$acc,
              DefaultValuedAttr<AIEI32Attr, "0">:$M,
              DefaultValuedAttr<AIEI32Attr, "0">:$N,
              DefaultValuedAttr<BoolAttr, "false">:$fmsub)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 multiply accumulate convolution";
   let description = [{
     AMD-specific multiply accumulate convolution intrinsic. Multiply accumulate convolution
@@ -388,8 +392,8 @@ def AIEVec_MinOp:
     Pure,
     AllTypesMatch<["lhs", "rhs", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector minimum";
   let description = [{
     AMD-specific intrinsic that calculates the minimum between two input vectors.
@@ -404,8 +408,8 @@ def AIEVec_MaxOp:
     Pure,
     AllTypesMatch<["lhs", "rhs", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector maximum";
   let description = [{
     AMD-specific intrinsic that calculates the maximum between two input vectors.
@@ -420,7 +424,8 @@ def AIEVec_CmpOp:
     Pure,
     AllTypesMatch<["lhs", "rhs"]>
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, DefaultValuedStrAttr<StrAttr, "">:$pred)>,
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
+             DefaultValuedStrAttr<StrAttr, "">:$pred)>,
   Results<(outs AnyUnsignedInteger:$result)> {
   let summary = "AIE vector comparison";
   let description = [{
@@ -449,8 +454,9 @@ def AIEVec_SelOp:
     Pure,
     AllTypesMatch<["lhs", "rhs", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$lhs, AnyVector:$rhs, AnyUnsignedInteger:$sel)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs,
+             AnyUnsignedInteger:$sel)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector lane wise selection";
   let description = [{
     AMD-specific intrinsic that performs lane wise selection between two input vectors, if a bit of sel is zero, the lane of vector lhs is selected, else the lane of vector rhs is selected.
@@ -465,7 +471,7 @@ def AIEVec_ExtElemOp:
     Pure,
     AllElementTypesMatch<["source", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$source, I32:$index)>,
+  Arguments<(ins AnyVectorOfNonZeroRank:$source, I32:$index)>,
   Results<(outs AnyTypeOf<[BF16, F32, I32, I16, I8]>:$result)> {
   let summary = "AIE extract element";
   let description =
@@ -481,8 +487,8 @@ def AIEVec_NegOp:
     Pure,
     AllTypesMatch<["source", "result"]>
   ]>,
-  Arguments<(ins AnyVector:$source)>,
-  Results<(outs AnyVector:$result)> {
+  Arguments<(ins AnyVectorOfNonZeroRank:$source)>,
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE vector negative";
   let description = [{
     AMD-specific intrinsic that negates the vector and returns the result.
@@ -622,7 +628,7 @@ def AIEVec_ShuffleOp : AIEVec_Op<"shuffle",
                       512, [I8, I16, I32, I64, I128, I256,
                             I512, BF16, F32]>>:$rhs,
                  AIEVec_ShuffleModeAttr:$mode)>,
-  Results<(outs AnyVector:$result)> {
+  Results<(outs AnyVectorOfNonZeroRank:$result)> {
   let summary = "AIE2 shuffle";
   let description = [{
     AMD AIEv2-specific vector shuffle. It performs a shuffle of the elements of
diff --git a/include/aie/Dialect/AIEVec/IR/AIEVecTypeConstraints.td b/include/aie/Dialect/AIEVec/IR/AIEVecTypeConstraints.td
index e74363c71a3..4cccb389965 100644
--- a/include/aie/Dialect/AIEVec/IR/AIEVecTypeConstraints.td
+++ b/include/aie/Dialect/AIEVec/IR/AIEVecTypeConstraints.td
@@ -47,7 +47,7 @@ class ShapedTypeBitWidth<string name> :
           # !subst(".getType()", "", ElementCount<name>.result) # ")">;
 
 class VectorOfBitWidthAndElementTypes<int bitwidth, list<Type> allowedTypes> :
-  Type<And<[VectorOf<allowedTypes>.predicate,
+  Type<And<[VectorOfNonZeroRankOf<allowedTypes>.predicate,
             CPred<ShapedTypeBitWidth<"_self">.result # " == " # bitwidth>]>,
        bitwidth # "-bit wide vector, of " # AnyTypeOf<allowedTypes>.summary>;
 
diff --git a/test/dialect/AIEVec/Transform/vectorize-contraction.mlir b/test/dialect/AIEVec/Transform/vectorize-contraction.mlir
index 5416acd22c8..a653422b0d2 100644
--- a/test/dialect/AIEVec/Transform/vectorize-contraction.mlir
+++ b/test/dialect/AIEVec/Transform/vectorize-contraction.mlir
@@ -34,13 +34,13 @@ module attributes {transform.with_named_sequence} {
 // CHECK-SAME: %[[A:.*]]: tensor<16x24xf32>
 // CHECK-SAME: %[[B:.*]]: tensor<24x16xf32>
 // CHECK-SAME: %[[C:.*]]: tensor<16x16xf32>
-// CHECK: %[[AM:.*]] = bufferization.to_memref %[[A]] : memref<16x24xf32>
+// CHECK: %[[AM:.*]] = bufferization.to_memref %[[A]] : tensor<16x24xf32> to memref<16x24xf32>
 // CHECK: %[[AVM:.*]] = vector.type_cast %[[AM]] : memref<16x24xf32> to memref<vector<16x24xf32>>
 // CHECK: %[[AV:.*]] = bufferization.to_tensor %[[AVM]] restrict : memref<vector<16x24xf32>>
-// CHECK: %[[BM:.*]] = bufferization.to_memref %[[B]] : memref<24x16xf32>
+// CHECK: %[[BM:.*]] = bufferization.to_memref %[[B]] : tensor<24x16xf32> to memref<24x16xf32>
 // CHECK: %[[BVM:.*]] = vector.type_cast %[[BM]] : memref<24x16xf32> to memref<vector<24x16xf32>>
 // CHECK: %[[BV:.*]] = bufferization.to_tensor %[[BVM]] restrict : memref<vector<24x16xf32>>
-// CHECK: %[[CM:.*]] = bufferization.to_memref %[[C]] : memref<16x16xf32>
+// CHECK: %[[CM:.*]] = bufferization.to_memref %[[C]] : tensor<16x16xf32> to memref<16x16xf32>
 // CHECK: %[[CVM:.*]] = vector.type_cast %[[CM]] : memref<16x16xf32> to memref<vector<16x16xf32>>
 // CHECK: %[[CV:.*]] = bufferization.to_tensor %[[CVM]] restrict : memref<vector<16x16xf32>>
 // CHECK: %[[RV:.*]] = linalg.generic {indexing_maps = [#[[NULLMAP]], #[[NULLMAP]], #[[NULLMAP]]],
@@ -54,7 +54,7 @@ module attributes {transform.with_named_sequence} {
 // CHECK-SAME:                                            : vector<16x24xf32>, vector<24x16xf32> into vector<16x16xf32>
 // CHECK:                   linalg.yield %[[RES]] : vector<16x16xf32>
 // CHECK:                  } -> tensor<vector<16x16xf32>>
-// CHECK: %[[RVM:.*]] = bufferization.to_memref %[[RV]] : memref<vector<16x16xf32>>
+// CHECK: %[[RVM:.*]] = bufferization.to_memref %[[RV]] : tensor<vector<16x16xf32>> to memref<vector<16x16xf32>>
 // CHECK: %[[RM:.*]] = vector.type_cast %[[RVM]] : memref<vector<16x16xf32>> to memref<16x16xf32>
 // CHECK: %[[R:.*]] = bufferization.to_tensor %[[RM]] restrict : memref<16x16xf32>
 // CHECK: return %[[R]] : tensor<16x16xf32>
@@ -95,13 +95,13 @@ module attributes {transform.with_named_sequence} {
 // CHECK-SAME: %[[A:.*]]: tensor<8x8x16x24xf32>
 // CHECK-SAME: %[[B:.*]]: tensor<8x8x24x16xf32>
 // CHECK-SAME: %[[C:.*]]: tensor<8x8x16x16xf32>
-// CHECK: %[[AM:.*]] = bufferization.to_memref %[[A]] : memref<8x8x16x24xf32>
+// CHECK: %[[AM:.*]] = bufferization.to_memref %[[A]] : tensor<8x8x16x24xf32> to memref<8x8x16x24xf32>
 // CHECK: %[[AVM:.*]] = vector.type_cast %[[AM]] : memref<8x8x16x24xf32> to memref<8x8xvector<16x24xf32>>
 // CHECK: %[[AV:.*]] = bufferization.to_tensor %[[AVM]] restrict : memref<8x8xvector<16x24xf32>>
-// CHECK: %[[BM:.*]] = bufferization.to_memref %[[B]] : memref<8x8x24x16xf32>
+// CHECK: %[[BM:.*]] = bufferization.to_memref %[[B]] : tensor<8x8x24x16xf32> to memref<8x8x24x16xf32>
 // CHECK: %[[BVM:.*]] = vector.type_cast %[[BM]] : memref<8x8x24x16xf32> to memref<8x8xvector<24x16xf32>>
 // CHECK: %[[BV:.*]] = bufferization.to_tensor %[[BVM]] restrict : memref<8x8xvector<24x16xf32>>
-// CHECK: %[[CM:.*]] = bufferization.to_memref %[[C]] : memref<8x8x16x16xf32>
+// CHECK: %[[CM:.*]] = bufferization.to_memref %[[C]] : tensor<8x8x16x16xf32> to memref<8x8x16x16xf32>
 // CHECK: %[[CVM:.*]] = vector.type_cast %[[CM]] : memref<8x8x16x16xf32> to memref<8x8xvector<16x16xf32>>
 // CHECK: %[[CV:.*]] = bufferization.to_tensor %[[CVM]] restrict : memref<8x8xvector<16x16xf32>>
 // CHECK: %[[RV:.*]] = linalg.generic {indexing_maps = [#[[PMAP]], #[[PMAP]], #[[PMAP]]],
@@ -115,7 +115,7 @@ module attributes {transform.with_named_sequence} {
 // CHECK-SAME:                                            : vector<16x24xf32>, vector<24x16xf32> into vector<16x16xf32>
 // CHECK:                   linalg.yield %[[RES]] : vector<16x16xf32>
 // CHECK:                  } -> tensor<8x8xvector<16x16xf32>>
-// CHECK: %[[RVM:.*]] = bufferization.to_memref %[[RV]] : memref<8x8xvector<16x16xf32>>
+// CHECK: %[[RVM:.*]] = bufferization.to_memref %[[RV]] : tensor<8x8xvector<16x16xf32>> to memref<8x8xvector<16x16xf32>>
 // CHECK: %[[RM:.*]] = vector.type_cast %[[RVM]] : memref<8x8xvector<16x16xf32>> to memref<8x8x16x16xf32>
 // CHECK: %[[R:.*]] = bufferization.to_tensor %[[RM]] restrict : memref<8x8x16x16xf32>
 // CHECK: return %[[R]] : tensor<8x8x16x16xf32>
@@ -158,13 +158,13 @@ module attributes {transform.with_named_sequence} {
 // CHECK-SAME: %[[A:.*]]: tensor<16x8x4x8xbf16>
 // CHECK-SAME: %[[B:.*]]: tensor<8x16x8x4xbf16>
 // CHECK-SAME: %[[C:.*]]: tensor<16x16x4x4xf32>
-// CHECK: %[[AM:.*]] = bufferization.to_memref %[[A]] : memref<16x8x4x8xbf16>
+// CHECK: %[[AM:.*]] = bufferization.to_memref %[[A]] : tensor<16x8x4x8xbf16> to memref<16x8x4x8xbf16>
 // CHECK: %[[AVM:.*]] = vector.type_cast %[[AM]] : memref<16x8x4x8xbf16> to memref<16x8xvector<4x8xbf16>>
 // CHECK: %[[AV:.*]] = bufferization.to_tensor %[[AVM]] restrict : memref<16x8xvector<4x8xbf16>>
-// CHECK: %[[BM:.*]] = bufferization.to_memref %[[B]] : memref<8x16x8x4xbf16>
+// CHECK: %[[BM:.*]] = bufferization.to_memref %[[B]] : tensor<8x16x8x4xbf16> to memref<8x16x8x4xbf16>
 // CHECK: %[[BVM:.*]] = vector.type_cast %[[BM]] : memref<8x16x8x4xbf16> to memref<8x16xvector<8x4xbf16>>
 // CHECK: %[[BV:.*]] = bufferization.to_tensor %[[BVM]] restrict : memref<8x16xvector<8x4xbf16>>
-// CHECK: %[[CM:.*]] = bufferization.to_memref %[[C]] : memref<16x16x4x4xf32>
+// CHECK: %[[CM:.*]] = bufferization.to_memref %[[C]] : tensor<16x16x4x4xf32> to memref<16x16x4x4xf32>
 // CHECK: %[[CVM:.*]] = vector.type_cast %[[CM]] : memref<16x16x4x4xf32> to memref<16x16xvector<4x4xf32>>
 // CHECK: %[[CV:.*]] = bufferization.to_tensor %[[CVM]] restrict : memref<16x16xvector<4x4xf32>>
 // CHECK: %[[RV:.*]] = linalg.generic {indexing_maps = [#[[AMAP]], #[[BMAP]], #[[CMAP]]],
@@ -180,7 +180,7 @@ module attributes {transform.with_named_sequence} {
 // CHECK-SAME:                                            : vector<4x8xf32>, vector<8x4xf32> into vector<4x4xf32>
 // CHECK:                   linalg.yield %[[RES]] : vector<4x4xf32>
 // CHECK:                  } -> tensor<16x16xvector<4x4xf32>>
-// CHECK: %[[RVM:.*]] = bufferization.to_memref %[[RV]] : memref<16x16xvector<4x4xf32>>
+// CHECK: %[[RVM:.*]] = bufferization.to_memref %[[RV]] : tensor<16x16xvector<4x4xf32>> to memref<16x16xvector<4x4xf32>>
 // CHECK: %[[RM:.*]] = vector.type_cast %[[RVM]] : memref<16x16xvector<4x4xf32>> to memref<16x16x4x4xf32>
 // CHECK: %[[R:.*]] = bufferization.to_tensor %[[RM]] restrict : memref<16x16x4x4xf32>
 // CHECK: return %[[R]] : tensor<16x16x4x4xf32>
diff --git a/utils/clone-llvm.sh b/utils/clone-llvm.sh
index c93b8102342..6e0f12c7ffb 100755
--- a/utils/clone-llvm.sh
+++ b/utils/clone-llvm.sh
@@ -13,8 +13,8 @@
 ##===----------------------------------------------------------------------===##
 
 # The LLVM commit to use.
-LLVM_PROJECT_COMMIT=0611a668d1389c8573e83eeafa6d5f6172c4cbc2
-DATETIME=2024111917
+LLVM_PROJECT_COMMIT=8da490320f6dcb99b4efef2cdb3d21002db1d2f7
+DATETIME=2024120316
 WHEEL_VERSION=20.0.0.$DATETIME+${LLVM_PROJECT_COMMIT:0:8}
 
 ############################################################################################