AMD extension: Bump to e240261

Upgrading llvm and stablehlo hash (onnx#3053)

* upgrading llvm and stablehlo hash. Fixing mlir tests

Signed-off-by: Christopher Munoz <[email protected]>

* fixing vector shapecast bug introduced by upgraded llvm

Signed-off-by: Christopher Munoz <[email protected]>

---------

Signed-off-by: Christopher Munoz <[email protected]>

Author: christopherlmunoz

docs/BuildOnLinuxOSX.md

@@ -15,7 +15,7 @@ Firstly, install MLIR (as a part of LLVM-Project):
 ``` bash
 git clone -n https://github.com/llvm/llvm-project.git
 # Check out a specific branch that is known to work with ONNX-MLIR.
-cd llvm-project && git checkout e8be3bea2ce0ec51b614cd7eb7d5d3a1e56d9524 && cd ..
+cd llvm-project && git checkout bb99503626b6efd2bd87a216ff279181cc6ec48f && cd ..
 ```
 
 [same-as-file]: <> (utils/build-mlir.sh)

docs/BuildOnWindows.md

@@ -52,7 +52,7 @@ Install MLIR (as a part of LLVM-Project):
 ```shell
 git clone -n https://github.com/llvm/llvm-project.git
 # Check out a specific branch that is known to work with ONNX-MLIR.
-cd llvm-project && git checkout e8be3bea2ce0ec51b614cd7eb7d5d3a1e56d9524 && cd ..
+cd llvm-project && git checkout bb99503626b6efd2bd87a216ff279181cc6ec48f && cd ..
 ```
 
 [same-as-file]: <> (utils/build-mlir.cmd)

src/Accelerators/NNPA/Conversion/ZLowToLLVM/ZLowToLLVMCommon.cpp

@@ -35,7 +35,7 @@ ApiRegistry RegisterAllApis(MLIRContext *context) {
   auto int16Ty = IntegerType::get(context, 16);
   auto int32Ty = IntegerType::get(context, 32);
   auto int64Ty = IntegerType::get(context, 64);
-  auto float32Ty = FloatType::getF32(context);
+  auto float32Ty = Float32Type::get(context);
 
   // Declare API type as an enum value, its string name and an LLVM Type
   // specifying its signature.
@@ -570,7 +570,7 @@ Type getZTensorStructTy(MLIRContext *context) {
   Type llvmI64Ty = IntegerType::get(context, 64);
   Type llvmI1Ty = IntegerType::get(context, 1);
   Type llvmI8Ty = IntegerType::get(context, 8);
-  Type llvmF32Ty = FloatType::getF32(context);
+  Type llvmF32Ty = Float32Type::get(context);
   Type llvmArray3I8Ty = LLVM::LLVMArrayType::get(llvmI8Ty, 3);
   Type llvmArray20I8Ty = LLVM::LLVMArrayType::get(llvmI8Ty, 20);
   Type llvmI8PtrTy = krnl::getPointerType(context, llvmI8Ty);
@@ -662,7 +662,7 @@ void fillInZTensor(PatternRewriter &rewriter, Location loc, ModuleOp module,
         scaleTy.isF32() && "Wrong type for zTensor's rec_scale. Must be float");
     create.llvm.store(recScale, recScalePtr);
   } else {
-    Value zero = create.llvm.constant(FloatType::getF32(context), (double)0.);
+    Value zero = create.llvm.constant(Float32Type::get(context), (double)0.);
     create.llvm.store(zero, recScalePtr);
   }
 
@@ -675,7 +675,7 @@ void fillInZTensor(PatternRewriter &rewriter, Location loc, ModuleOp module,
         offsetTy.isF32() && "Wrong type for zTensor's offset. Must be float");
     create.llvm.store(offset, offsetPtr);
   } else {
-    Value zero = create.llvm.constant(FloatType::getF32(context), (double)0.);
+    Value zero = create.llvm.constant(Float32Type::get(context), (double)0.);
     create.llvm.store(zero, offsetPtr);
   }
 

src/Conversion/KrnlToLLVM/ConvertKrnlToLLVM.cpp

@@ -193,12 +193,23 @@ void populateAffineAndKrnlToLLVMConversion(RewritePatternSet &patterns,
   // They run it in two steps, and add additional lowerings.
 
   vector::populateVectorToVectorCanonicalizationPatterns(patterns);
+  vector::populateVectorBitCastLoweringPatterns(patterns);
   vector::populateVectorBroadcastLoweringPatterns(patterns);
   vector::populateVectorContractLoweringPatterns(
       patterns, vector::VectorTransformsOptions());
+  vector::populateVectorMaskOpLoweringPatterns(patterns);
+  vector::populateVectorShapeCastLoweringPatterns(patterns);
+  vector::populateVectorInterleaveLoweringPatterns(patterns);
   vector::populateVectorTransposeLoweringPatterns(
       patterns, vector::VectorTransformsOptions());
-  vector::populateVectorShapeCastLoweringPatterns(patterns);
+  // Vector transfer ops with rank > 1 should be lowered with VectorToSCF.
+  vector::populateVectorTransferLoweringPatterns(
+      patterns, /*maxTransferRank=*/1);
+  vector::populateVectorMaskMaterializationPatterns(
+      patterns, /*force32BitVectorIndices*/ false);
+  vector::populateVectorInsertExtractStridedSliceTransforms(patterns);
+  vector::populateVectorStepLoweringPatterns(patterns);
+  vector::populateVectorRankReducingFMAPattern(patterns);
 
   populateAffineToStdConversionPatterns(patterns);
   populateSCFToControlFlowConversionPatterns(patterns);

src/Conversion/KrnlToLLVM/KrnlRandomNormal.cpp

@@ -80,10 +80,10 @@ class KrnlRandomNormalOpLowering : public ConversionPattern {
     // or
     //  (memref<3x4x5xf64>, index, f64, f64, f64)
     Type llvmVoidTy = LLVM::LLVMVoidType::get(context);
-    Type llvmOptionsTy = FloatType::getF32(context);
+    Type llvmOptionsTy = Float32Type::get(context);
     Type llvmOutputTy = getPointerType(context, llvmOptionsTy);
     if (inType.isF64()) {
-      llvmOptionsTy = FloatType::getF64(context);
+      llvmOptionsTy = Float64Type::get(context);
       llvmOutputTy = getPointerType(context, llvmOptionsTy);
     }
     Type llvmI64Ty = IntegerType::get(context, 64);

src/Conversion/KrnlToLLVM/KrnlUnaryMath.cpp

@@ -172,19 +172,19 @@ class KrnlUnaryMathOpLowering : public ConversionPattern {
     Type outType = op->getResultTypes().front();
     Type llvmInType, llvmOutType;
     if (inType.isF16())
-      llvmInType = FloatType::getF16(context);
+      llvmInType = Float16Type::get(context);
     else if (inType.isF32())
-      llvmInType = FloatType::getF32(context);
+      llvmInType = Float32Type::get(context);
     else if (inType.isF64())
-      llvmInType = FloatType::getF64(context);
+      llvmInType = Float64Type::get(context);
     else if (inType.isBF16())
-      llvmInType = FloatType::getBF16(context);
+      llvmInType = BFloat16Type::get(context);
     if (outType.isInteger(1))
       llvmOutType = IntegerType::get(context, 1);
     else if (outType.isF32())
-      llvmOutType = FloatType::getF32(context);
+      llvmOutType = Float32Type::get(context);
     else if (outType.isF64())
-      llvmOutType = FloatType::getF64(context);
+      llvmOutType = Float64Type::get(context);
 
     // Insert and/or get reference to elementary math function declaration.
     assert(

src/Conversion/ONNXToKrnl/Math/LRN.cpp

@@ -52,7 +52,7 @@ struct ONNXLRNOpLowering : public OpConversionPattern<ONNXLRNOp> {
     float alphaLit = adaptor.getAlpha().convertToFloat();
     float betaLit = adaptor.getBeta().convertToFloat();
     int sizeLit = adaptor.getSize();
-    auto f32Type = FloatType::getF32(rewriter.getContext());
+    auto f32Type = Float32Type::get(rewriter.getContext());
     Value biasValue = create.math.constant(f32Type, biasLit);
     Value alphaDivSizeValue =
         create.math.constant(f32Type, alphaLit / static_cast<float>(sizeLit));

src/Conversion/ONNXToTOSA/Math/Conv2D.cpp

@@ -34,7 +34,7 @@ Value createConvInGroups(PatternRewriter &rewriter, Operation *op,
     const llvm::ArrayRef<int64_t> weightShape, Value &newInput,
     Value &newWeight, Value &bias, const int64_t groups,
     DenseI64ArrayAttr &pads, DenseI64ArrayAttr &strides,
-    DenseI64ArrayAttr &dilations) {
+    DenseI64ArrayAttr &dilations, TypeAttr &accType) {
   // Set up constants outside of loop
   const int64_t sizeOfSliceInput = weightShape[1];
   const int64_t sizeOfSliceKernel = weightShape[0] / groups;
@@ -65,7 +65,7 @@ Value createConvInGroups(PatternRewriter &rewriter, Operation *op,
         mlir::cast<ShapedType>(resultType).getElementType());
     Value tempConv2D = tosa::CreateOpAndInfer<mlir::tosa::Conv2DOp>(rewriter,
         op->getLoc(), newConvOutputType, newSliceInput, newSliceWeight,
-        newSliceBias, pads, strides, dilations);
+        newSliceBias, pads, strides, dilations, accType);
     // Add value to vector
     sliceValues.push_back(tempConv2D);
   }
@@ -156,6 +156,10 @@ class ONNXConvOpLoweringToTOSA : public ConversionPattern {
 
     DenseI64ArrayAttr newPads = rewriter.getDenseI64ArrayAttr(reorderedPads);
 
+    Type convType =
+        (resultType.isF16()) ? rewriter.getF16Type() : rewriter.getF32Type();
+    TypeAttr accType = mlir::TypeAttr::get(convType);
+
     // Handle group parameter by creating multiple convs
     const int64_t group = adaptor.getGroup();
     Value conv2D = NULL;
@@ -166,10 +170,10 @@ class ONNXConvOpLoweringToTOSA : public ConversionPattern {
 
       conv2D = tosa::CreateOpAndInfer<mlir::tosa::Conv2DOp>(rewriter,
           convOp->getLoc(), newConvOutputType, newInput, newWeight, bias,
-          newPads, strides, dilations);
+          newPads, strides, dilations, accType);
     } else {
       auto inputChannels = inputType.getDimSize(1);
-      auto outputChannels = resultType.cast<ShapedType>().getDimSize(1);
+      auto outputChannels = cast<ShapedType>(resultType).getDimSize(1);
       if (group == inputChannels && (outputChannels % inputChannels == 0)) {
         // If the group == inputChannels and
         // outputChannels == inputChannels * integerNumber,
@@ -185,19 +189,19 @@ class ONNXConvOpLoweringToTOSA : public ConversionPattern {
 
         Type newConvOutputType = RankedTensorType::get(
             llvm::SmallVector<int64_t, 4>(4, ShapedType::kDynamic),
-            resultType.cast<ShapedType>().getElementType());
+            cast<ShapedType>(resultType).getElementType());
 
         conv2D = tosa::CreateOpAndInfer<mlir::tosa::DepthwiseConv2DOp>(rewriter,
             convOp->getLoc(), newConvOutputType, newInput, newWeight, bias,
-            newPads, strides, dilations);
+            newPads, strides, dilations, accType);
       } else if (group <= groupedConvThreshold) {
         // Decompose group convolution into a concatenation of tosa.conv2d ops
         // can be costly, so only allow it when the number of groups is less
         // than configurable threshold.
 
         conv2D = createConvInGroups(rewriter, convOp, tosaBuilder, resultType,
             weightShape, newInput, newWeight, bias, group, newPads, strides,
-            dilations);
+            dilations, accType);
       } else {
         return rewriter.notifyMatchFailure(
             op, "this type of grouped Conv is not supported");

src/Conversion/ONNXToTOSA/ONNXToTOSALegalizeUtils.cpp

@@ -114,7 +114,7 @@ mlir::Value buildOnnxToTosaPaddingConstOp(mlir::PatternRewriter &rewriter,
 
   // Create a new pad vec in the right format
   // ONNX : [b1, b2, b3, b4, e1, e2, e3, e4]
-  // TOSA :[[b1, e1], [b2, e2], [b3, e3], [b4, e4]]
+  // TOSA :[b1, e1, b2, e2, b3, e3, b4, e4]
 
   // Adds any initial or last vals, not included in onnxPads.
   llvm::SmallVector<int64_t, 8> tosaPads{initialVals};
@@ -125,11 +125,9 @@ mlir::Value buildOnnxToTosaPaddingConstOp(mlir::PatternRewriter &rewriter,
     tosaPads.push_back(onnxPads[i + dimSize]);
   }
   tosaPads.insert(tosaPads.end(), lastVals.begin(), lastVals.end());
-
-  // TOSA format groups dimensions by 2.
-  const unsigned int numberOfDims = tosaPads.size() / 2;
   TosaBuilder tosaBuilder(rewriter, loc);
-  return tosaBuilder.getConst(tosaPads, {numberOfDims, 2});
+  return tosaBuilder.getConst(
+      tosaPads, {static_cast<int64_t>(tosaPads.size())});
 }
 
 mlir::Value expandShape(mlir::PatternRewriter &rewriter, mlir::Location loc,

src/Conversion/ONNXToTOSA/Tensor/Expand.cpp

@@ -25,6 +25,7 @@
 #include <mlir/IR/BuiltinTypeInterfaces.h>
 #include <mlir/IR/BuiltinTypes.h>
 #include <mlir/Transforms/DialectConversion.h>
+#include <mlir/Dialect/Tosa/Utils/ConversionUtils.h>
 
 #include <llvm/ADT/SmallVector.h>
 #include <llvm/Support/Casting.h>
@@ -86,8 +87,8 @@ class ONNXExpandLoweringToTOSA : public OpConversionPattern<ONNXExpandOp> {
       newInput = tosaBuilder.reshape(adaptor.getInput(), newShape);
     }
 
-    auto denseShape =
-        getMultiplies(op, cast<RankedTensorType>(newInput.getType()).getShape(),
+    const auto multiplies =
+        getMultiplies(cast<RankedTensorType>(newInput.getType()).getShape(),
             outputType.getShape());
     auto resultElementType = cast<RankedTensorType>(inputType).getElementType();
     auto newResultElementType =
@@ -101,8 +102,9 @@ class ONNXExpandLoweringToTOSA : public OpConversionPattern<ONNXExpandOp> {
         llvm::SmallVector<int64_t>(
             outputType.getShape().size(), ShapedType::kDynamic),
         newResultElementType);
-    onnx_mlir::tosa::CreateReplaceOpAndInfer<mlir::tosa::TileOp>(
-        rewriter, op, newTileOutputType, newInput, denseShape);
+    onnx_mlir::tosa::CreateReplaceOpAndInfer<mlir::tosa::TileOp>(rewriter, op,
+        newTileOutputType, newInput,
+        mlir::tosa::getTosaConstShape(rewriter, op->getLoc(), multiplies));
     return success();
   }
 
@@ -148,7 +150,7 @@ class ONNXExpandLoweringToTOSA : public OpConversionPattern<ONNXExpandOp> {
     return result;
   }
 
-  static DenseI64ArrayAttr getMultiplies(ONNXExpandOp &op,
+  static llvm::SmallVector<int64_t> getMultiplies(
       const llvm::ArrayRef<int64_t> &inputShape,
       const llvm::ArrayRef<int64_t> &outputShape) {
     llvm::SmallVector<int64_t> multipliesArray;
@@ -159,7 +161,7 @@ class ONNXExpandLoweringToTOSA : public OpConversionPattern<ONNXExpandOp> {
         multipliesArray.push_back(outputShape[i] / inputShape[i]);
       }
     }
-    return DenseI64ArrayAttr::get(op.getContext(), multipliesArray);
+    return multipliesArray;
   }
 };