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boards: amd: Add support for AMD MicroBlaze V
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with OCM(128kB) and DDR(2G) memories, cpu, interrupt controller, timers and uartlite console. Flash is not yet supported. Provided DT is describing one basic configuration which is subset of initial QEMU configuration. CPU is connected to secondary interrupt controller, timer and uartlite for communication over serial line. In soc.c there is no reason to check MULTI_LEVEL_INTERRUPTS or adding dependency on XLNX_INTC because different configuration is not supported today. ARCH_CPU_IDLE_CUSTOM is enabled because default HW design is not enabling C_USE_SLEEP configuration option. Also Wakeup pins are not connected from interrupt controller that's why wake up is not happening. This is limitation for now. Signed-off-by: Michal Simek <[email protected]> Link: zephyrproject-rtos/zephyr#80379 State: waiting
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‎boards/amd/mbv32/Kconfig.defconfig‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#

‎boards/amd/mbv32/Kconfig.mbv32‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_MBV32
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select SOC_MBV32
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if BOARD_MBV32
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config MULTI_LEVEL_INTERRUPTS
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default y
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config 2ND_LEVEL_INTERRUPTS
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default y
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config MAX_IRQ_PER_AGGREGATOR
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default 32
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endif

‎boards/amd/mbv32/board.cmake‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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set(SUPPORTED_EMU_PLATFORMS qemu)
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set(QEMU_ARCH riscv32)
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set(QEMU_CPU_TYPE_${ARCH} riscv32)
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set(QEMU_FLAGS_${ARCH}
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-machine amd-microblaze-v-virt
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-nographic
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-net nic,netdev=eth0 -netdev user,id=eth0 -net nic,netdev=eth1 -netdev user,id=eth1
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-m 2g
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)
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set(QEMU_KERNEL_OPTION
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-device loader,cpu-num=0,file=\$<TARGET_FILE:\${logical_target_for_zephyr_elf}>
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)

‎boards/amd/mbv32/board.yml‎

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board:
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name: mbv32
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vendor: amd
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socs:
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- name: mbv32

‎boards/amd/mbv32/mbv32.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for AMD MicroBlaze V
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*
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* (C) Copyright 2024, Advanced Micro Devices, Inc.
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*
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* Michal Simek <[email protected]>
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "AMD MicroBlaze V 32bit";
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compatible = "qemu,mbv", "amd,mbv";
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <100000000>;
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cpu_0: cpu@0 {
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compatible = "amd,mbv32", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32imafdc";
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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clock-frequency = <100000000>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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aliases {
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serial0 = &uart0;
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};
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chosen {
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bootargs = "earlycon=sbi console=ttyUL0,115200";
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stdout-path = "serial0:115200n8";
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &ram0;
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};
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ram0: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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lmb0: memory@0 {
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compatible = "mmio-sram";
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reg = <0 0x20000>;
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};
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clk100: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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axi: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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bootph-all;
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axi_intc: interrupt-controller@41200000 {
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compatible = "xlnx,xps-intc-1.00.a";
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reg = <0x41200000 0x1000>;
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interrupt-controller;
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interrupt-parent = <&cpu0_intc>;
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#interrupt-cells = <2>;
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interrupts-extended = <&cpu0_intc 11>;
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xlnx,kind-of-intr = <0x1a>;
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xlnx,num-intr-inputs = <11>;
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};
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xlnx_timer0: timer@41c00000 {
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compatible = "amd,xps-timer-1.00.a";
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reg = <0x41c00000 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <0 2>;
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xlnx,one-timer-only = <0>;
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clocks = <&clk100>;
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};
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uart0: serial@40600000 {
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compatible = "xlnx,xps-uartlite-1.00.a";
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reg = <0x40600000 0x1000>;
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interrupt-parent = <&axi_intc>;
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interrupts = <1 2>;
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clocks = <&clk100>;
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current-speed = <115200>;
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};
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};
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};

‎boards/amd/mbv32/mbv32.yaml‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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identifier: mbv32
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name: MBV32 softcore CPU
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type: mcu
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simulation: qemu
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arch: riscv
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toolchain:
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- zephyr
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ram: 2097152
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testing:
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ignore_tags:
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- bluetooth
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- coredump
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- crypto
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- jwt
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- logging
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- lwm2m
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- mcumgr
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- sensor
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- shell
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- smf
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- tinycrypt
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- xip
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- zdsp
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vendor: amd

‎boards/amd/mbv32/mbv32_defconfig‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_XIP=n
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
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CONFIG_HEAP_MEM_POOL_SIZE=4096

‎soc/xlnx/mbv32/CMakeLists.txt‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(
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${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S
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${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S
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soc.c
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)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

‎soc/xlnx/mbv32/Kconfig‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_MBV32
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select RISCV
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select ATOMIC_OPERATIONS_C
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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imply ARCH_CPU_IDLE_CUSTOM
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select CLOCK_CONTROL
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select CLOCK_CONTROL_FIXED_RATE_CLOCK
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select CONSOLE
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select SERIAL
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select UART_CONSOLE if (UART_NS16550 || UART_XLNX_UARTLITE)
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select UART_INTERRUPT_DRIVEN if (UART_NS16550 || UART_XLNX_UARTLITE)
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imply UART_NS16550 if DT_HAS_NS16550_ENABLED
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imply UART_XLNX_UARTLITE if DT_HAS_UARTLITE_ENABLED
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imply GPIO if DT_HAS_XLNX_XPS_GPIO_1_00_A_ENABLED
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imply GPIO_XLNX_AXI if DT_HAS_XLNX_XPS_GPIO_1_00_A_ENABLED
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imply AMD_TMRCTR if DT_HAS_AMD_XPS_TIMER_1_00_A_ENABLED
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imply XLNX_INTC if DT_HAS_XLNX_XPS_INTC_1_00_A_ENABLED
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select XLNX_INTC_USE_IPR if XLNX_INTC
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select XLNX_INTC_USE_SIE if XLNX_INTC
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select XLNX_INTC_USE_CIE if XLNX_INTC
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select XLNX_INTC_USE_IVR if XLNX_INTC

‎soc/xlnx/mbv32/Kconfig.defconfig‎

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#
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# Copyright (c) 2024 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_MBV32
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config MBV_CSR_DATA_WIDTH
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int "Select Control/Status register width"
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default 32
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config NUM_IRQS
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default 44
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endif # SOC_MBV32

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