boards: amd: mbv32: Fix riscv,isa property

By default fd extensions are not enabled in MB-V core. As of now,
source code is not working with these extensions, hence remove
them from riscv,isa property. Also, while at it, update riscv,isa
with zicsr and zifencei extensions (enabled in default MB-V core)

Signed-off-by: Mubin Sayyed <[email protected]>
Message-ID: <[email protected]>
State: pending

Author: mubinsyed2

boards/amd/mbv32/mbv32.dts

@@ -23,7 +23,7 @@
 			compatible = "amd,mbv32", "riscv";
 			device_type = "cpu";
 			reg = <0>;
-			riscv,isa = "rv32imafdc";
+			riscv,isa = "rv32imac_zicsr_zifencei";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;