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| 1 | +.. mbv32: |
| 2 | +
|
| 3 | +AMD mbv32 |
| 4 | +######### |
| 5 | + |
| 6 | +Overview |
| 7 | +******** |
| 8 | + |
| 9 | +mbv32 board is based on Microblaze V design preset example from AMD Vivado™ Design Suite targeted |
| 10 | +for "AMD Kintex UltraScale FPGA KCU105" evaluation kit. Said design preset example is build |
| 11 | +with realtime configuration (with fast interrupt disabled). Example design system consist of |
| 12 | +following IP blocks: |
| 13 | + |
| 14 | +.. code-block:: console |
| 15 | +
|
| 16 | + AMD Microblaze V processsor core FPGA IP |
| 17 | + AXI INTC FPGA IP |
| 18 | + AXI Timer FPGA IP |
| 19 | + AXI I2C FPGA IP |
| 20 | + AXI UARTLITE FPGA IP |
| 21 | + AXI GPIO FPGA IP |
| 22 | + AXI QSPI FPGA IP |
| 23 | +
|
| 24 | +Also, it consist of following memory blocks, |
| 25 | + |
| 26 | +.. code-block:: console |
| 27 | +
|
| 28 | + Local BRAM Memory (128 KB) |
| 29 | + DDR Memory (2 GB) |
| 30 | +
|
| 31 | +mbv32 realtime example design |
| 32 | +============================= |
| 33 | + |
| 34 | +Prebuilt mbv32 example design system is available in AMD Vivado™ Design Suite. It can be also found |
| 35 | +at AMD Microblaze RISC-V wiki page. It consist of bitstream file needed for FPGA configuration. |
| 36 | + |
| 37 | +Download Zephyr elf file and run application |
| 38 | +============================================ |
| 39 | + |
| 40 | +To download the Zephyr Executable and Linkable Format .elf file, please use following west command. |
| 41 | + |
| 42 | +.. code-block:: console |
| 43 | +
|
| 44 | + west flash --runner xsdb --elf-file mbv32/zephyr/zephyr.elf --bitstream <path>/system.bit |
| 45 | +
|
| 46 | +References |
| 47 | +========== |
| 48 | + |
| 49 | +- `AMD MicroBlaze™ V Processor`_ |
| 50 | +- `AMD Vivado™ Design Suite`_ |
| 51 | +- `AMD Kintex UltraScale FPGA KCU105 Evaluation Kit`_ |
| 52 | + |
| 53 | +.. _AMD MicroBlaze™ V Processor: |
| 54 | + https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html |
| 55 | + |
| 56 | +.. _AMD Vivado™ Design Suite: |
| 57 | + https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html |
| 58 | + |
| 59 | +.. _AMD Kintex UltraScale FPGA KCU105 Evaluation Kit: |
| 60 | + https://www.xilinx.com/products/boards-and-kits/kcu105.html |
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