SIP_CST mapping fails for top level ports with array length of one #424
Description
I'm trying to use the SiP HyperRAM on the Tang Nano 4K (GW1NSR-LV4CQN48PC6/I5) with Litex.
After adding the IO port wrangling for the gowin toolchain to the apicula target as well, the generated verilog has the following ports (which seems to work for the original Toolchain, but I don't have access to it):
module sipeed_tang_nano_4k (
inout wire [7:0] IO_hpram_dq, /* synthesis syn_tristate = 1 */
inout wire [0:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */
output wire [0:0] O_hpram_ck,
output wire [0:0] O_hpram_ck_n,
output wire [0:0] O_hpram_cs_n,
output wire [0:0] O_hpram_reset_n,
(* keep = "true" *)
input wire clk27,
input wire serial_rx,
output reg serial_tx,
input wire user_btn0,
output wire user_led0
);
Unfortunately this mapping fails:
Info: Pack IOBs...
ERROR: Unconstrained IO:O_hpram_reset_n_OBUF_O
After checking the chipdb, where the pins have indices to 1, I've tried with an array of length 2 instead:
module sipeed_tang_nano_4k (
inout wire [7:0] IO_hpram_dq, /* synthesis syn_tristate = 1 */
inout wire [1:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */
output wire [1:0] O_hpram_ck,
output wire [1:0] O_hpram_ck_n,
output wire [1:0] O_hpram_cs_n,
output wire [1:0] O_hpram_reset_n,
(* keep = "true" *)
input wire clk27,
input wire serial_rx,
output reg serial_tx,
input wire user_btn0,
output wire user_led0
);
and this fixed the pin constraints. (Unfortunately nextpnr still fails with Warning: Failed to find a route for arc 140 of net $PACKER_GND.)
Looking at the json generated by yosys, the main difference seems to be that the bits field in the ports has a length of 2 instead of 1 (and all the other changes associated with that). I think that yosys handles arrays and wires in the ports identically, but nextpnr maps arrays of length 1 to the name so it doesn't match the constraint for e.g. O_hpram_ck_n[0].
A possible solution might be to add the constraints for the port name without an index as well, e.g. duplicating the one for O_hpram_ck_n[0] for O_hpram_ck_n.
I've used nextpnr-himbaechel and yosys from oss-cad-suite 2025-11-11.