DQS

DQS

Ports

Port	Size	Direction
DLLSTEP	8	input
DQSIN	1	input
DQSR90	1	output
DQSW0	1	output
DQSW270	1	output
FCLK	1	input
HOLD	1	input
PCLK	1	input
RBURST	1	output
RCLKSEL	3	input
RDIR	1	input
READ	4	input
RESET	1	input
RFLAG	1	output
RLOADN	1	input
RMOVE	1	input
RPOINT	3	output
RVALID	1	output
WDIR	1	input
WFLAG	1	output
WLOADN	1	input
WMOVE	1	input
WPOINT	3	output
WSTEP	8	input

Parameters

Parameter	Default Value
DQS_MODE	X1
FIFO_MODE_SEL	0 (0b0)
HWL	false
RD_PNTR	0 (0b000)

Verilog Instantiation

DQS #(
    .DQS_MODE(DQS_MODE),
    .FIFO_MODE_SEL(FIFO_MODE_SEL),
    .HWL(HWL),
    .RD_PNTR(RD_PNTR)
) dqs_inst (
    .DLLSTEP(DLLSTEP),
    .DQSIN(DQSIN),
    .DQSR90(DQSR90),
    .DQSW0(DQSW0),
    .DQSW270(DQSW270),
    .FCLK(FCLK),
    .HOLD(HOLD),
    .PCLK(PCLK),
    .RBURST(RBURST),
    .RCLKSEL(RCLKSEL),
    .RDIR(RDIR),
    .READ(READ),
    .RESET(RESET),
    .RFLAG(RFLAG),
    .RLOADN(RLOADN),
    .RMOVE(RMOVE),
    .RPOINT(RPOINT),
    .RVALID(RVALID),
    .WDIR(WDIR),
    .WFLAG(WFLAG),
    .WLOADN(WLOADN),
    .WMOVE(WMOVE),
    .WPOINT(WPOINT),
    .WSTEP(WSTEP)
);