Cluster or constrain on cell that might have multiple options

[KelvinChung2000]

I have implemented an architecture with a few bels of the same type but with different routing patterns within a tile/CLB. For example, the tile has 2 input FF (z=1, 2) connected to a LUT (z=0), and the output of the LUT is connected to another FF (z=3). How can I pack/constrain the cells in the circuit such that input FF to the LUT can be picked between z=1 and 2 but not placed at the output FF (z=3)?