LFE5U-45F-6TQ144 EHXPLLL_UR does not work

[mixing-man]

Made a simple project with one PLL but there is no output and PLL is not locked. PLL is located at X89/Y4.
When adding a 2nd PLL the 1st one starts working and the 2nd doesn't create any output because this one is now at X89/Y4 and the other (1st) at X88/Y70.
No idea how to debug this.

Forcing use of other PLLs in the device results in the following:

(* BEL="X1/Y4/EHXPLL_UL" *) -> does not work
(* BEL="X2/Y70/EHXPLL_LL" *) -> ok
(* BEL="X88/Y70/EHXPLL_LR" *) -> ok

So it seems both upper PLLs are not implemented correctly in this device.

plltest.zip

[gatecat]

Thanks for the issue and the testcase! Do you happen to have quick access to Diamond? Does it let you place three PLLs on this device/package combo or does it give some kind of error? If not, no worries, I'll set it up again myself to have a look.

[mixing-man]

Diamond implements 3 PLLs just fine.

diamond_3pll_test.tar.gz