write_verilog: support $buf and $barrier

georgerennie · georgerennie · commit 0465fe07eae2 · 2024-11-20T17:45:59.000+01:00
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
@@ -1071,7 +1071,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == ID($_BUF_)) {
+	if (cell->type.in(ID($buf), ID($_BUF_), ID($barrier))) {
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort(ID::Y));
 		f << stringf(" = ");

Original file line number	Diff line number	Diff line change
`@@ -1071,7 +1071,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)`
`1071`	`1071`	`return true;`
`1072`	`1072`	`}`
`1073`	`1073`
`1074`		`- if (cell->type == ID($_BUF_)) {`
	`1074`	`+ if (cell->type.in(ID($buf), ID($_BUF_), ID($barrier))) {`
`1075`	`1075`	`f << stringf("%s" "assign ", indent.c_str());`
`1076`	`1076`	`dump_sigspec(f, cell->getPort(ID::Y));`
`1077`	`1077`	`f << stringf(" = ");`