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KrystalDelusionKrystalDelusion
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Reduce comparisons of size_t and int
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
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9 files changed

+59
-59
lines changed

9 files changed

+59
-59
lines changed

‎backends/edif/edif.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -338,7 +338,7 @@ struct EdifBackend : public Backend {
338338
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
339339
else {
340340
std::string hex_string = "";
341-
for (size_t i = 0; i < val.size(); i += 4) {
341+
for (auto i = 0; i < val.size(); i += 4) {
342342
int digit_value = 0;
343343
if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1;
344344
if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2;

‎frontends/ast/ast.cc‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -931,21 +931,21 @@ bool AstNode::bits_only_01() const
931931
RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
932932
{
933933
RTLIL::State extbit = bits.back();
934-
while (width > int(bits.size()))
934+
while (width > GetSize(bits))
935935
bits.push_back(extbit);
936936
return RTLIL::Const(bits);
937937
}
938938

939939
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
940940
{
941941
std::vector<RTLIL::State> bits = this->bits;
942-
if (width >= 0 && width < int(bits.size()))
942+
if (width >= 0 && width < GetSize(bits))
943943
bits.resize(width);
944-
if (width >= 0 && width > int(bits.size())) {
944+
if (width >= 0 && width > GetSize(bits)) {
945945
RTLIL::State extbit = RTLIL::State::S0;
946946
if ((is_signed || is_unsized) && !bits.empty())
947947
extbit = bits.back();
948-
while (width > int(bits.size()))
948+
while (width > GetSize(bits))
949949
bits.push_back(extbit);
950950
}
951951
return RTLIL::Const(bits);
@@ -1029,7 +1029,7 @@ double AstNode::asReal(bool is_signed)
10291029
val = const_neg(val, val, false, false, val.size());
10301030

10311031
double v = 0;
1032-
for (size_t i = 0; i < val.size(); i++)
1032+
for (auto i = 0; i < val.size(); i++)
10331033
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
10341034
// the net or the variable shall be treated as zero upon conversion.
10351035
if (val.at(i) == RTLIL::State::S1)

‎frontends/ast/genrtlil.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -984,7 +984,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
984984
// unallocated enum, ignore
985985
break;
986986
case AST_CONSTANT:
987-
width_hint = max(width_hint, int(bits.size()));
987+
width_hint = max(width_hint, GetSize(bits));
988988
if (!is_signed)
989989
sign_hint = false;
990990
break;

‎frontends/ast/simplify.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3493,7 +3493,7 @@ skip_dynamic_range_lvalue_expansion:;
34933493
delete buf;
34943494

34953495
uint32_t result = 0;
3496-
for (size_t i = 0; i < arg_value.size(); i++)
3496+
for (auto i = 0; i < arg_value.size(); i++)
34973497
if (arg_value.at(i) == RTLIL::State::S1)
34983498
result = i + 1;
34993499

@@ -4339,7 +4339,7 @@ replace_fcall_later:;
43394339
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
43404340
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
43414341
log_assert(a.size() == b.size());
4342-
for (size_t i = 0; i < a.size(); i++)
4342+
for (auto i = 0; i < a.size(); i++)
43434343
if (a[i] != b[i])
43444344
a.bits()[i] = RTLIL::State::Sx;
43454345
newNode = mkconst_bits(a.to_bits(), sign_hint);

‎kernel/calc.cc‎

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
3333
if (arg.size() > 0 && is_signed)
3434
padding = arg.back();
3535

36-
while (int(arg.size()) < width)
36+
while (GetSize(arg) < width)
3737
arg.bits().push_back(padding);
3838

3939
arg.bits().resize(width);
@@ -45,15 +45,15 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
4545

4646
BigInteger::Sign sign = BigInteger::positive;
4747
State inv_sign_bit = RTLIL::State::S1;
48-
size_t num_bits = val.size();
48+
auto num_bits = val.size();
4949

5050
if (as_signed && num_bits && val[num_bits-1] == RTLIL::State::S1) {
5151
inv_sign_bit = RTLIL::State::S0;
5252
sign = BigInteger::negative;
5353
num_bits--;
5454
}
5555

56-
for (size_t i = 0; i < num_bits; i++)
56+
for (auto i = 0; i < num_bits; i++)
5757
if (val[i] == RTLIL::State::S0 || val[i] == RTLIL::State::S1)
5858
mag.setBit(i, val[i] == inv_sign_bit);
5959
else if (undef_bit_pos < 0)
@@ -78,12 +78,12 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
7878
if (val.getSign() < 0)
7979
{
8080
mag--;
81-
for (int i = 0; i < result_len; i++)
81+
for (auto i = 0; i < result_len; i++)
8282
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
8383
}
8484
else
8585
{
86-
for (int i = 0; i < result_len; i++)
86+
for (auto i = 0; i < result_len; i++)
8787
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
8888
}
8989
}
@@ -132,14 +132,14 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b)
132132
RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
133133
{
134134
if (result_len < 0)
135-
result_len = arg1.size();
135+
result_len = GetSize(arg1);
136136

137137
RTLIL::Const arg1_ext = arg1;
138138
extend_u0(arg1_ext, result_len, signed1);
139139

140140
RTLIL::Const result(RTLIL::State::Sx, result_len);
141-
for (size_t i = 0; i < size_t(result_len); i++) {
142-
if (i >= arg1_ext.size())
141+
for (auto i = 0; i < result_len; i++) {
142+
if (i >= GetSize(arg1_ext))
143143
result.bits()[i] = RTLIL::State::S0;
144144
else if (arg1_ext.bits()[i] == RTLIL::State::S0)
145145
result.bits()[i] = RTLIL::State::S1;
@@ -154,15 +154,15 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
154154
RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
155155
{
156156
if (result_len < 0)
157-
result_len = max(arg1.size(), arg2.size());
157+
result_len = max(GetSize(arg1), GetSize(arg2));
158158

159159
extend_u0(arg1, result_len, signed1);
160160
extend_u0(arg2, result_len, signed2);
161161

162162
RTLIL::Const result(RTLIL::State::Sx, result_len);
163-
for (size_t i = 0; i < size_t(result_len); i++) {
164-
RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0;
165-
RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0;
163+
for (auto i = 0; i < result_len; i++) {
164+
RTLIL::State a = i < GetSize(arg1) ? arg1.bits()[i] : RTLIL::State::S0;
165+
RTLIL::State b = i < GetSize(arg2) ? arg2.bits()[i] : RTLIL::State::S0;
166166
result.bits()[i] = logic_func(a, b);
167167
}
168168

@@ -193,11 +193,11 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log
193193
{
194194
RTLIL::State temp = initial;
195195

196-
for (size_t i = 0; i < arg1.size(); i++)
196+
for (auto i = 0; i < arg1.size(); i++)
197197
temp = logic_func(temp, arg1[i]);
198198

199199
RTLIL::Const result(temp);
200-
while (int(result.size()) < result_len)
200+
while (GetSize(result) < result_len)
201201
result.bits().push_back(RTLIL::State::S0);
202202
return result;
203203
}
@@ -240,7 +240,7 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const
240240
BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
241241
RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
242242

243-
while (int(result.size()) < result_len)
243+
while (GetSize(result) < result_len)
244244
result.bits().push_back(RTLIL::State::S0);
245245
return result;
246246
}
@@ -255,7 +255,7 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const
255255
RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
256256
RTLIL::Const result(logic_and(bit_a, bit_b));
257257

258-
while (int(result.size()) < result_len)
258+
while (GetSize(result) < result_len)
259259
result.bits().push_back(RTLIL::State::S0);
260260
return result;
261261
}
@@ -270,7 +270,7 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const
270270
RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
271271
RTLIL::Const result(logic_or(bit_a, bit_b));
272272

273-
while (int(result.size()) < result_len)
273+
while (GetSize(result) < result_len)
274274
result.bits().push_back(RTLIL::State::S0);
275275
return result;
276276
}
@@ -286,7 +286,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
286286
BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction;
287287

288288
if (result_len < 0)
289-
result_len = arg1.size();
289+
result_len = GetSize(arg1);
290290

291291
RTLIL::Const result(RTLIL::State::Sx, result_len);
292292
if (undef_bit_pos >= 0)
@@ -296,7 +296,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
296296
BigInteger pos = BigInteger(i) + offset;
297297
if (pos < 0)
298298
result.bits()[i] = vacant_bits;
299-
else if (pos >= BigInteger(int(arg1.size())))
299+
else if (pos >= BigInteger(GetSize(arg1)))
300300
result.bits()[i] = sign_ext ? arg1.back() : vacant_bits;
301301
else
302302
result.bits()[i] = arg1[pos.toInt()];
@@ -347,7 +347,7 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
347347
bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
348348
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
349349

350-
while (int(result.size()) < result_len)
350+
while (GetSize(result) < result_len)
351351
result.bits().push_back(RTLIL::State::S0);
352352
return result;
353353
}
@@ -358,7 +358,7 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
358358
bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
359359
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
360360

361-
while (int(result.size()) < result_len)
361+
while (GetSize(result) < result_len)
362362
result.bits().push_back(RTLIL::State::S0);
363363
return result;
364364
}
@@ -369,12 +369,12 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
369369
RTLIL::Const arg2_ext = arg2;
370370
RTLIL::Const result(RTLIL::State::S0, result_len);
371371

372-
int width = max(arg1_ext.size(), arg2_ext.size());
372+
int width = max(GetSize(arg1_ext), GetSize(arg2_ext));
373373
extend_u0(arg1_ext, width, signed1 && signed2);
374374
extend_u0(arg2_ext, width, signed1 && signed2);
375375

376376
RTLIL::State matched_status = RTLIL::State::S1;
377-
for (size_t i = 0; i < arg1_ext.size(); i++) {
377+
for (auto i = 0; i < arg1_ext.size(); i++) {
378378
if (arg1_ext.at(i) == RTLIL::State::S0 && arg2_ext.at(i) == RTLIL::State::S1)
379379
return result;
380380
if (arg1_ext.at(i) == RTLIL::State::S1 && arg2_ext.at(i) == RTLIL::State::S0)
@@ -403,11 +403,11 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
403403
RTLIL::Const arg2_ext = arg2;
404404
RTLIL::Const result(RTLIL::State::S0, result_len);
405405

406-
int width = max(arg1_ext.size(), arg2_ext.size());
406+
int width = max(GetSize(arg1_ext), GetSize(arg2_ext));
407407
extend_u0(arg1_ext, width, signed1 && signed2);
408408
extend_u0(arg2_ext, width, signed1 && signed2);
409409

410-
for (size_t i = 0; i < arg1_ext.size(); i++) {
410+
for (auto i = 0; i < arg1_ext.size(); i++) {
411411
if (arg1_ext.at(i) != arg2_ext.at(i))
412412
return result;
413413
}
@@ -432,7 +432,7 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
432432
bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
433433
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
434434

435-
while (int(result.size()) < result_len)
435+
while (GetSize(result) < result_len)
436436
result.bits().push_back(RTLIL::State::S0);
437437
return result;
438438
}
@@ -443,7 +443,7 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
443443
bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
444444
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
445445

446-
while (int(result.size()) < result_len)
446+
while (GetSize(result) < result_len)
447447
result.bits().push_back(RTLIL::State::S0);
448448
return result;
449449
}
@@ -452,21 +452,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2
452452
{
453453
int undef_bit_pos = -1;
454454
BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
455-
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos);
455+
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), undef_bit_pos);
456456
}
457457

458458
RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
459459
{
460460
int undef_bit_pos = -1;
461461
BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
462-
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos);
462+
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), undef_bit_pos);
463463
}
464464

465465
RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
466466
{
467467
int undef_bit_pos = -1;
468468
BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
469-
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
469+
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
470470
}
471471

472472
// truncating division
@@ -480,7 +480,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
480480
bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
481481
a = a.getSign() == BigInteger::negative ? -a : a;
482482
b = b.getSign() == BigInteger::negative ? -b : b;
483-
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
483+
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
484484
}
485485

486486
// truncating modulo
@@ -494,7 +494,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
494494
bool result_neg = a.getSign() == BigInteger::negative;
495495
a = a.getSign() == BigInteger::negative ? -a : a;
496496
b = b.getSign() == BigInteger::negative ? -b : b;
497-
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
497+
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
498498
}
499499

500500
RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@@ -516,7 +516,7 @@ RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const
516516
// bigint division with negative numbers is wonky, make sure we only negate at the very end
517517
result = -((a + b - 1) / b);
518518
}
519-
return big2const(result, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
519+
return big2const(result, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
520520
}
521521

522522
RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@@ -539,7 +539,7 @@ RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const
539539
} else {
540540
modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b;
541541
}
542-
return big2const(modulo, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
542+
return big2const(modulo, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
543543
}
544544

545545
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@@ -590,7 +590,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
590590
y *= -1;
591591
}
592592

593-
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
593+
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
594594
}
595595

596596
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
@@ -626,7 +626,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2
626626
return arg2;
627627

628628
RTLIL::Const ret = arg1;
629-
for (int i = 0; i < ret.size(); i++)
629+
for (auto i = 0; i < ret.size(); i++)
630630
if (ret[i] != arg2[i])
631631
ret.bits()[i] = State::Sx;
632632
return ret;
@@ -640,7 +640,7 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
640640
if (!arg3.is_onehot())
641641
return RTLIL::Const(State::Sx, arg1.size());
642642

643-
for (int i = 0; i < arg3.size(); i++)
643+
for (auto i = 0; i < arg3.size(); i++)
644644
if (arg3[i] == State::S1)
645645
return RTLIL::Const(std::vector<RTLIL::State>(arg2.begin() + i*arg1.size(), arg2.begin() + (i+1)*arg1.size()));
646646

@@ -702,7 +702,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar
702702
{
703703
log_assert(arg2.size() == arg1.size());
704704
RTLIL::Const result(RTLIL::State::S0, arg1.size());
705-
for (int i = 0; i < arg1.size(); i++)
705+
for (auto i = 0; i < arg1.size(); i++)
706706
result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0;
707707

708708
return result;
@@ -713,7 +713,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
713713
log_assert(arg2.size() == arg1.size());
714714
log_assert(arg3.size() == arg1.size());
715715
RTLIL::Const result(RTLIL::State::Sx, arg1.size());
716-
for (int i = 0; i < arg1.size(); i++) {
716+
for (auto i = 0; i < arg1.size(); i++) {
717717
if (arg3[i] != State::Sx || arg1[i] == arg2[i])
718718
result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i];
719719
}

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