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1 parent cba9460 commit 23922faCopy full SHA for 23922fa
tests/various/tcl_apis.tcl
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+yosys read_verilog tcl_apis.v
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+
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+if {[rtlil::get_attr -string -mod top foo] != "bar"} {
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+ error "bad top module attribute"
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+}
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+if {[rtlil::get_attr -bool top w dont_touch] != 1} {
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+ error "bad w wire attribute"
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+if {[rtlil::get_param -int top inst PARAM] != 4} {
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+ error "bad parameter"
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+rtlil::set_attr -true -mod top marked
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+yosys select -assert-any A:marked
tests/various/tcl_apis.v
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+module m;
+parameter PARAM = 0;
+endmodule
+(* foo="bar" *)
+module top;
+ (* dont_touch *)
+ wire w;
+ m #(.PARAM(4)) inst();
tests/various/tcl_apis.ys
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+yosys tcl tcl_apis.tcl
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