create testcase to check correct addition of areas.

Author: cwalter

tests/various/stat.ys

@@ -15,20 +15,35 @@ stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.
 
 
 design -reset
-read_rtlil <<EOT
+read_rtlil << EOT
 module \top
   wire input 1 \A
   wire output 2 \Y
-  wire output 3 \NY
+  wire output 3 \N
+
+  cell \sg13g2_and2_1 \sub1
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+
   cell \child \sequential
     connect \A \A
     connect \B 1'0
     connect \R 1'0
     connect \Y \Y
-    connect \NY \NY
+    connect \N \N
   end
 
-  cell \sg13g2_and2_1 \sub
+  cell \child \sequential1
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \N \N
+  end
+
+  cell \sg13g2_and2_1 \sub2
     connect \A \A
     connect \B 1'0
     connect \Y \Y
@@ -41,19 +56,19 @@ module \child
   wire input 3 \R
 
   wire output 4 \Y
-  wire output 5 \NY
-  cell \sg13g2_dfrbp_1 
+  wire output 5 \N
+
+  cell \sg13g2_dfrbp_1 \sequential_ff
     connect \CLK \A
     connect \D \B
     connect \Q \Y
-    connect \Q_N \NY
+    connect \Q_N \N
     connect \RESET_B \R
   end
 
-  
 end
 EOT
-logger -expect log "Chip area for module '\\top': 63.504000" 1
-logger -expect log "of which used for sequential elements: 54.432000 (85.71%) " 1
+logger -expect log "Chip area for top module '\\top': 112.492800" 1
+logger -expect log "of which used for sequential elements: 94.348800" 1
 logger -expect-no-warnings
-stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top