File tree Expand file tree Collapse file tree 1 file changed +6
-2
lines changed Expand file tree Collapse file tree 1 file changed +6
-2
lines changed Original file line number Diff line number Diff line change @@ -10,8 +10,11 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
1010 reg [WORD:0 ] data_out_r;
1111 reg [WORD:0 ] memory [0 :DEPTH];
1212
13- integer i,j = 64'hF4B1CA8127865242 ;
14- initial
13+ integer i,j;
14+ // Initialize in initial block as a workaround for
15+ // https://github.com/YosysHQ/yosys/issues/4792
16+ initial begin
17+ j = 64'hF4B1CA8127865242 ;
1518 for (i = 0 ; i <= DEPTH; i++ ) begin
1619 // In case this ROM will be implemented in fabric: fill the memory with some data
1720 // uncorrelated with the address, or Yosys might see through the ruse and e.g. not
@@ -21,6 +24,7 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
2124 j = j ^ (j << 25 );
2225 j = j ^ (j >> 27 );
2326 end
27+ end
2428
2529 always @(posedge clk) begin
2630 data_out_r <= memory[address_in];
You can’t perform that action at this time.
0 commit comments