Skip to content

Commit 76379d9

Browse files
docs: Initial documentation for generated help
Very briefly on command help Mostly focused on v1 and v2 of the cell help, but still largely bullet points
1 parent 3d35f36 commit 76379d9

File tree

1 file changed

+160
-0
lines changed

1 file changed

+160
-0
lines changed

docs/source/yosys_internals/extending_yosys/contributing.rst

Lines changed: 160 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,3 +34,163 @@ for implicit type casts, always use ``GetSize(foobar)`` instead of
3434
``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`)
3535

3636
Use range-based for loops whenever applicable.
37+
38+
Generated help messages and documentation
39+
-----------------------------------------
40+
41+
Command help
42+
~~~~~~~~~~~~
43+
44+
- `help` without arguments
45+
46+
- lists all commands with their ``Pass::short_help``
47+
48+
- ``help <command>``
49+
50+
- calls ``Pass::help()`` for ``<command>``
51+
52+
.. note::
53+
54+
A more expressive way to generate formatted help messages is `in
55+
development`_.
56+
57+
.. _in development: https://github.com/YosysHQ/yosys/pull/4860
58+
59+
Cell help
60+
~~~~~~~~~
61+
62+
- :file:`techlibs/common/simcells.v` and :file:`techlibs/common/simlib.v`
63+
- parsed by :file:`techlibs/common/cellhelp.py`
64+
- comments preceding cell type converted to a ``SimHelper`` struct, defined in
65+
:file:`kernel/register.cc`
66+
- ``#include``d in :file:`kernel/register.cc`, creating a map of cell types to
67+
their ``SimHelper`` struct.
68+
69+
- ``help -cells``
70+
71+
- lists all cells with their input/output ports
72+
73+
- ``help <celltype>``
74+
75+
- prints help message for ``<celltype>``
76+
- constructed from ``SimHelper`` content depending on version
77+
78+
- ``help <celltype>+``
79+
80+
- prints verilog code for ``<celltype>``
81+
82+
v1 (default)
83+
^^^^^^^^^^^^
84+
85+
- Legacy format
86+
- Expects formatting as follows:
87+
88+
.. code-block:: verilog
89+
90+
//-
91+
//- $<celltype> (<ports>)
92+
//* group <cellgroup>
93+
//-
94+
//- <cell description>
95+
//-
96+
module \$<celltype> (<ports>);
97+
// ...
98+
endmodule
99+
100+
- ``//* group`` line is generally after the cell signature, but can appear
101+
anywhere in the comment block
102+
103+
- determines where the cell is included in sphinx
104+
- check :file:`docs/source/cell` for current groups
105+
- a missing group will raise an error
106+
- assigning an unused group will result in the cell not being included in the
107+
sphinx docs
108+
109+
- the port signature line (``//- $<celltype> (<ports>)``) must start with (at
110+
least) 4 spaces (not tabs)
111+
112+
- the empty lines (``//-``) before/after the signature are required
113+
114+
- cell description can be multiple lines, but each line must start with ``//-``
115+
and a space
116+
117+
- description should have a trailing empty line
118+
- line breaks are preserved in `help` calls but will be rendered as text in
119+
sphinx docs, with empty lines being required between paragraphs
120+
121+
- cells in :file:`techlibs/common/simcells.v` can have optional truth table at
122+
the end of the cell description which is rendered in sphinx docs as a literal
123+
code block
124+
- e.g. `$_NOT_`:
125+
126+
.. code-block:: verilog
127+
128+
//-
129+
//- $_NOT_ (A, Y)
130+
//* group comb_simple
131+
//-
132+
//- An inverter gate.
133+
//-
134+
//- Truth table: A | Y
135+
//- ---+---
136+
//- 0 | 1
137+
//- 1 | 0
138+
//-
139+
140+
v2 (more expressive)
141+
^^^^^^^^^^^^^^^^^^^^
142+
143+
- each field of the ``SimHelper`` struct can be assigned with:
144+
145+
.. code-block:: verilog
146+
147+
//* <name> <value>
148+
149+
- ``ver`` must be explicitly set as ``2``
150+
- optional fields ``title`` and ``tags``
151+
152+
- title used for better displaying of cell
153+
- tags is a space-separated list of :doc:`/cell/properties`
154+
155+
- the port signature is automatically generated from the ``module`` definition
156+
- cell description is the same as v1
157+
- can link to commands or passes using backticks (`````)
158+
- e.g. `$nex`:
159+
160+
.. code-block:: verilog
161+
162+
//* ver 2
163+
//* title Case inequality
164+
//* group binary
165+
//* tags x-aware
166+
//- This corresponds to the Verilog '!==' operator.
167+
//-
168+
//- Refer to `$eqx` for more details.
169+
//-
170+
171+
- code blocks can be included as following:
172+
173+
.. code-block:: verilog
174+
175+
//- text
176+
//- ::
177+
//-
178+
//- monospaced text
179+
//-
180+
//- indentation and line length will be preserved, giving a scroll bar if necessary for the browser window
181+
//-
182+
//- more text
183+
184+
- the empty line after the ``::`` and before the text continues are required
185+
- the ``::`` line will be ignored in the `help` call while sphinx docs will
186+
treat everything that follows as a literal block until the next unindented
187+
line:
188+
189+
text
190+
::
191+
192+
monospaced text
193+
194+
indentation and line length will be preserved, giving a scroll bar if necessary for the browser window
195+
196+
more text

0 commit comments

Comments
 (0)