techmap: wrap builtin $lcu as golden module in PPA tests

Author: widlarizer

tests/techmap/han-carlson.tcl

@@ -1,7 +1,7 @@
 yosys -import
 
 read_verilog +/choices/han-carlson.v
-read_verilog lcu_refined.v
+read_verilog -icells lcu_refined.v
 design -save init
 
 for {set i 1} {$i <= 16} {incr i} {

tests/techmap/kogge-stone.tcl

@@ -1,7 +1,7 @@
 yosys -import
 
 read_verilog +/choices/kogge-stone.v
-read_verilog lcu_refined.v
+read_verilog -icells lcu_refined.v
 design -save init
 
 for {set i 1} {$i <= 16} {incr i} {

tests/techmap/lcu_refined.v

@@ -1,20 +1,13 @@
-// Copied from techlibs/common/simlib.v
-// with this condition removed: (^{P, G, CI} !== 1'bx)
 module lcu (P, G, CI, CO);
+	parameter WIDTH = 2;
 
-parameter WIDTH = 2;
+	input [WIDTH-1:0] P, G;
+	input CI;
 
-input [WIDTH-1:0] P;    // Propagate
-input [WIDTH-1:0] G;    // Generate
-input CI;               // Carry-in
+	output [WIDTH-1:0] CO;
 
-output reg [WIDTH-1:0] CO; // Carry-out
+	reg [WIDTH-1:0] p, g;
 
-integer i;
-always @* begin
-	CO[0] = G[0] || (P[0] && CI);
-	for (i = 1; i < WIDTH; i = i+1)
-		CO[i] = G[i] || (P[i] && CO[i-1]);
-end
+	\$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO));
 
 endmodule