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1 parent 0072a26 commit aac562dCopy full SHA for aac562d
backends/aiger/aiger.cc
@@ -153,6 +153,9 @@ struct AigerWriter
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sigmap.add(wire);
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// handle ports
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+ // provided the input_bits and output_bits don't get sorted they
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+ // will be returned in reverse order, so add them in reverse to
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+ // match
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for (auto riter = module->ports.rbegin(); riter != module->ports.rend(); ++riter) {
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auto *wire = module->wire(*riter);
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for (int i = 0; i < GetSize(wire); i++)
@@ -353,6 +356,7 @@ struct AigerWriter
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}
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init_map.sort();
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+ // we are relying here on unsorted pools iterating last-in-first-out
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if (!no_sort) {
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input_bits.sort();
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output_bits.sort();
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