@@ -83,19 +83,23 @@ struct ModIndex : public RTLIL::Monitor
8383
8484 void port_add (RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
8585 {
86- for (int i = 0 ; i < GetSize (sig); i++) {
87- RTLIL::SigBit bit = sigmap (sig[i]);
86+ int i = 0 ;
87+ for (auto &sig_bit : sig) {
88+ RTLIL::SigBit bit = sigmap (sig_bit);
8889 if (bit.wire )
8990 database[bit].ports .insert (PortInfo (cell, port, i));
91+ ++i;
9092 }
9193 }
9294
9395 void port_del (RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
9496 {
95- for (int i = 0 ; i < GetSize (sig); i++) {
96- RTLIL::SigBit bit = sigmap (sig[i]);
97+ int i = 0 ;
98+ for (auto &sig_bit : sig) {
99+ RTLIL::SigBit bit = sigmap (sig_bit);
97100 if (bit.wire )
98101 database[bit].ports .erase (PortInfo (cell, port, i));
102+ ++i;
99103 }
100104 }
101105
@@ -179,10 +183,11 @@ struct ModIndex : public RTLIL::Monitor
179183 if (auto_reload_module)
180184 return ;
181185
182- for (int i = 0 ; i < GetSize (sigsig.first ); i++)
186+ RTLIL::SigSpecConstIterator second_it = sigsig.second .begin ();
187+ for (auto &first_bit : sigsig.first )
183188 {
184- RTLIL::SigBit lhs = sigmap (sigsig. first [i] );
185- RTLIL::SigBit rhs = sigmap (sigsig. second [i] );
189+ RTLIL::SigBit lhs = sigmap (first_bit );
190+ RTLIL::SigBit rhs = sigmap (*second_it++ );
186191 bool has_lhs = database.count (lhs) != 0 ;
187192 bool has_rhs = database.count (rhs) != 0 ;
188193
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