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1 | 1 | add_library(yosys_passes_pmgen INTERFACE) |
2 | 2 |
|
3 | | -function(pmgen_command _name) |
| 3 | +function(pmgen_command _name _path) |
4 | 4 | add_custom_command( |
5 | | - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h |
6 | | - COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h -p ${_name} ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg |
7 | | - DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg |
8 | | - COMMENT "Generating passes/pmgen/${_name}_pm.h..." |
| 5 | + OUTPUT ${CMAKE_BINARY_DIR}/${_path}/${_name}_pm.h |
| 6 | + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${CMAKE_BINARY_DIR}/${_path}/${_name}_pm.h -p ${_name} ${CMAKE_SOURCE_DIR}/${_path}/${_name}.pmg |
| 7 | + DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py ${CMAKE_SOURCE_DIR}/${_path}/${_name}.pmg |
| 8 | + COMMENT "Generating ${_path}/${_name}_pm.h..." |
9 | 9 | ) |
10 | 10 | endfunction() |
11 | 11 |
|
12 | | -pmgen_command(test_pmgen) |
13 | | -pmgen_command(ice40_dsp) |
14 | | -pmgen_command(ice40_wrapcarry) |
15 | | -pmgen_command(xilinx_dsp) |
16 | | -pmgen_command(xilinx_dsp48a) |
17 | | -pmgen_command(xilinx_dsp_CREG) |
18 | | -pmgen_command(xilinx_dsp_cascade) |
19 | | -pmgen_command(microchip_dsp) |
20 | | -pmgen_command(microchip_dsp_CREG) |
21 | | -pmgen_command(microchip_dsp_cascade) |
22 | | -pmgen_command(xilinx_srl) |
| 12 | +pmgen_command(test_pmgen passes/pmgen) |
| 13 | +pmgen_command(ice40_dsp techlibs/ice40) |
| 14 | +pmgen_command(ice40_wrapcarry techlibs/ice40) |
| 15 | +pmgen_command(xilinx_dsp techlibs/xilinx) |
| 16 | +pmgen_command(xilinx_dsp48a techlibs/xilinx) |
| 17 | +pmgen_command(xilinx_dsp_CREG techlibs/xilinx) |
| 18 | +pmgen_command(xilinx_dsp_cascade techlibs/xilinx) |
| 19 | +pmgen_command(microchip_dsp techlibs/microchip) |
| 20 | +pmgen_command(microchip_dsp_CREG techlibs/microchip) |
| 21 | +pmgen_command(microchip_dsp_cascade techlibs/microchip) |
| 22 | +pmgen_command(xilinx_srl techlibs/xilinx) |
23 | 23 |
|
24 | 24 | add_custom_command( |
25 | | - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/peepopt_pm.h |
26 | | - COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${CMAKE_CURRENT_BINARY_DIR}/peepopt_pm.h -p peepopt |
27 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_right.pmg |
28 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_left.pmg |
29 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftadd.pmg |
30 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_muldiv.pmg |
31 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_formal_clockgateff.pmg |
| 25 | + OUTPUT ${CMAKE_BINARY_DIR}/passes/opt/peepopt_pm.h |
| 26 | + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${CMAKE_BINARY_DIR}/passes/opt/peepopt_pm.h -p peepopt |
| 27 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_shiftmul_right.pmg |
| 28 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_shiftmul_left.pmg |
| 29 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_shiftadd.pmg |
| 30 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_muldiv.pmg |
| 31 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_muldiv_c.pmg |
| 32 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_formal_clockgateff.pmg |
32 | 33 | DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py |
33 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_right.pmg |
34 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_left.pmg |
35 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftadd.pmg |
36 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_muldiv.pmg |
37 | | - ${CMAKE_CURRENT_SOURCE_DIR}/peepopt_formal_clockgateff.pmg |
| 34 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_shiftmul_right.pmg |
| 35 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_shiftmul_left.pmg |
| 36 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_shiftadd.pmg |
| 37 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_muldiv.pmg |
| 38 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_muldiv_c.pmg |
| 39 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt_formal_clockgateff.pmg |
38 | 40 | COMMENT "Generating passes/pmgen/peepopt_pm.h..." |
39 | 41 | ) |
40 | 42 |
|
41 | 43 | target_sources(yosys_passes_pmgen INTERFACE |
42 | 44 | test_pmgen.cc |
43 | | - ice40_dsp.cc |
44 | | - ice40_wrapcarry.cc |
45 | | - xilinx_dsp.cc |
46 | | - microchip_dsp.cc |
47 | | - peepopt.cc |
48 | | - xilinx_srl.cc |
| 45 | + ${CMAKE_SOURCE_DIR}/techlibs/ice40/ice40_dsp.cc |
| 46 | + ${CMAKE_SOURCE_DIR}/techlibs/ice40/ice40_wrapcarry.cc |
| 47 | + ${CMAKE_SOURCE_DIR}/techlibs/xilinx/xilinx_dsp.cc |
| 48 | + ${CMAKE_SOURCE_DIR}/techlibs/microchip/microchip_dsp.cc |
| 49 | + ${CMAKE_SOURCE_DIR}/passes/opt/peepopt.cc |
| 50 | + ${CMAKE_SOURCE_DIR}/techlibs/xilinx/xilinx_srl.cc |
49 | 51 | ) |
50 | 52 |
|
51 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/test_pmgen_pm.h) |
| 53 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/passes/pmgen/test_pmgen_pm.h) |
52 | 54 |
|
53 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ice40_dsp_pm.h) |
54 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ice40_wrapcarry_pm.h) |
| 55 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/ice40/ice40_dsp_pm.h) |
| 56 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/ice40/ice40_wrapcarry_pm.h) |
55 | 57 |
|
56 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp_pm.h) |
57 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp48a_pm.h) |
58 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp_CREG_pm.h) |
59 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp_cascade_pm.h) |
| 58 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_pm.h) |
| 59 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/xilinx/xilinx_dsp48a_pm.h) |
| 60 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_CREG_pm.h) |
| 61 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_cascade_pm.h) |
60 | 62 |
|
61 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/microchip_dsp_pm.h) |
62 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/microchip_dsp_CREG_pm.h) |
63 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/microchip_dsp_cascade_pm.h) |
| 63 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/microchip/microchip_dsp_pm.h) |
| 64 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/microchip/microchip_dsp_CREG_pm.h) |
| 65 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/microchip/microchip_dsp_cascade_pm.h) |
64 | 66 |
|
65 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/peepopt_pm.h) |
| 67 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/passes/opt/peepopt_pm.h) |
66 | 68 |
|
67 | | -target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_srl_pm.h) |
| 69 | +target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_BINARY_DIR}/techlibs/xilinx/xilinx_srl_pm.h) |
68 | 70 |
|
69 | 71 | target_link_libraries(yosys PRIVATE yosys_passes_pmgen) |
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