write_verilog: support $barrier

georgerennie · georgerennie · commit ba7efe67a353 · 2025-07-10T15:43:17.000+01:00
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
@@ -1096,7 +1096,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.in(ID($_BUF_), ID($buf))) {
+	if (cell->type.in(ID($_BUF_), ID($buf), ID($barrier))) {
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort(ID::Y));
 		f << stringf(" = ");

Original file line number	Diff line number	Diff line change
`@@ -1096,7 +1096,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)`
`1096`	`1096`	`return true;`
`1097`	`1097`	`}`
`1098`	`1098`
`1099`		`- if (cell->type.in(ID($_BUF_), ID($buf))) {`
	`1099`	`+ if (cell->type.in(ID($_BUF_), ID($buf), ID($barrier))) {`
`1100`	`1100`	`f << stringf("%s" "assign ", indent.c_str());`
`1101`	`1101`	`dump_sigspec(f, cell->getPort(ID::Y));`
`1102`	`1102`	`f << stringf(" = ");`