Skip to content

Commit c18fbd4

Browse files
committed
opt_dff: sigmap bits before looking up muxes
1 parent 08479a0 commit c18fbd4

File tree

1 file changed

+23
-12
lines changed

1 file changed

+23
-12
lines changed

passes/opt/opt_dff.cc

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include "passes/techmap/simplemap.h"
3030
#include <stdio.h>
3131
#include <stdlib.h>
32+
#include <optional>
3233

3334
USING_YOSYS_NAMESPACE
3435
PRIVATE_NAMESPACE_BEGIN
@@ -95,6 +96,18 @@ struct OptDffWorker
9596

9697
}
9798

99+
// If this bit sigmaps to a bit driven by a mux ouput bit that only drives this
100+
// bit, returns that mux otherwise nullopt
101+
std::optional<cell_int_t> mergeable_mux(SigBit bit) {
102+
sigmap.apply(bit);
103+
auto it = bit2mux.find(bit);
104+
105+
if (it == bit2mux.end() || bitusers[bit] != 1)
106+
return std::nullopt;
107+
108+
return it->second;
109+
}
110+
98111
State combine_const(State a, State b) {
99112
if (a == State::Sx && !opt.keepdc)
100113
return b;
@@ -591,13 +604,12 @@ struct OptDffWorker
591604
State reset_val = State::Sx;
592605
if (ff.has_srst)
593606
reset_val = ff.val_srst[i];
594-
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
595-
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
596-
if (GetSize(mbit.first->getPort(ID::S)) != 1)
607+
while (const auto mbit = mergeable_mux(ff.sig_d[i])) {
608+
if (GetSize(mbit->first->getPort(ID::S)) != 1)
597609
break;
598-
SigBit s = mbit.first->getPort(ID::S);
599-
SigBit a = mbit.first->getPort(ID::A)[mbit.second];
600-
SigBit b = mbit.first->getPort(ID::B)[mbit.second];
610+
SigBit s = mbit->first->getPort(ID::S);
611+
SigBit a = mbit->first->getPort(ID::A)[mbit->second];
612+
SigBit b = mbit->first->getPort(ID::B)[mbit->second];
601613
// Workaround for funny memory WE pattern.
602614
if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
603615
break;
@@ -668,13 +680,12 @@ struct OptDffWorker
668680
for (int i = 0 ; i < ff.width; i++) {
669681
// First, eat up as many simple muxes as possible.
670682
ctrls_t enables;
671-
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
672-
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
673-
if (GetSize(mbit.first->getPort(ID::S)) != 1)
683+
while (const auto mbit = mergeable_mux(ff.sig_d[i])) {
684+
if (GetSize(mbit->first->getPort(ID::S)) != 1)
674685
break;
675-
SigBit s = mbit.first->getPort(ID::S);
676-
SigBit a = mbit.first->getPort(ID::A)[mbit.second];
677-
SigBit b = mbit.first->getPort(ID::B)[mbit.second];
686+
SigBit s = mbit->first->getPort(ID::S);
687+
SigBit a = mbit->first->getPort(ID::A)[mbit->second];
688+
SigBit b = mbit->first->getPort(ID::B)[mbit->second];
678689
if (a == ff.sig_q[i]) {
679690
enables.insert(ctrl_t(s, true));
680691
ff.sig_d[i] = b;

0 commit comments

Comments
 (0)