@@ -60,6 +60,7 @@ struct FlattenWorker
6060 bool ignore_wb = false ;
6161 bool create_scopeinfo = true ;
6262 bool create_scopename = false ;
63+ bool barriers = false ;
6364
6465 template <class T >
6566 void map_attributes (RTLIL::Cell *cell, T *object, IdString orig_object_name)
@@ -246,7 +247,27 @@ struct FlattenWorker
246247 log_error (" Cell port %s.%s.%s is driving constant bits: %s <= %s\n " ,
247248 log_id (module ), log_id (cell), log_id (port_it.first ), log_signal (new_conn.first ), log_signal (new_conn.second ));
248249
249- module ->connect (new_conn);
250+ if (barriers) {
251+ // Drive public output wires with barriers and the rest with
252+ // connections
253+ RTLIL::SigSig skip_conn, barrier_conn;
254+
255+ for (int i = 0 ; i < GetSize (new_conn.first ); i++) {
256+ const auto lhs = new_conn.first [i], rhs = new_conn.second [i];
257+ auto & sigsig = !lhs.is_wire () || !lhs.wire ->name .isPublic () ? skip_conn : barrier_conn;
258+ sigsig.first .append (lhs);
259+ sigsig.second .append (rhs);
260+ }
261+
262+ if (!skip_conn.first .empty ())
263+ module ->connect (skip_conn);
264+
265+ if (!barrier_conn.first .empty ())
266+ module ->addBarrier (NEW_ID, barrier_conn.second , barrier_conn.first );
267+ } else {
268+ module ->connect (new_conn);
269+ }
270+
250271 sigmap.add (new_conn.first , new_conn.second );
251272 }
252273
@@ -345,6 +366,10 @@ struct FlattenPass : public Pass {
345366 log (" with a public name the enclosing scope can be found via their\n " );
346367 log (" 'hdlname' attribute.\n " );
347368 log (" \n " );
369+ log (" -barriers\n " );
370+ log (" Use $barrier cells to connect flattened modules to their surrounding\n " );
371+ log (" scope instead of connections for public wires.\n " );
372+ log (" \n " );
348373 }
349374 void execute (std::vector<std::string> args, RTLIL::Design *design) override
350375 {
@@ -367,6 +392,10 @@ struct FlattenPass : public Pass {
367392 worker.create_scopename = true ;
368393 continue ;
369394 }
395+ if (args[argidx] == " -barriers" ) {
396+ worker.barriers = true ;
397+ continue ;
398+ }
370399 break ;
371400 }
372401 extra_args (args, argidx, design);
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