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mmickommicko
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Merge pull request #4806 from YosysHQ/micko/verific_blackbox
verific: Disable module existence check during static elaboration
2 parents 481162b + 0539888 commit d0f239a

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3 files changed

+104
-23
lines changed

3 files changed

+104
-23
lines changed

‎frontends/verific/verific.cc‎

Lines changed: 46 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -2688,11 +2688,51 @@ struct VerificExtNets
26882688
}
26892689
};
26902690

2691+
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
2692+
static msg_type_t prev_1063;
2693+
#endif
2694+
#ifdef VERIFIC_VHDL_SUPPORT
2695+
static msg_type_t prev_1240 ;
2696+
static msg_type_t prev_1241 ;
2697+
#endif
2698+
void save_blackbox_msg_state()
2699+
{
2700+
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
2701+
prev_1063 = Message::GetMessageType("VERI-1063") ;
2702+
Message::SetMessageType("VERI-1063", VERIFIC_INFO);
2703+
#endif
2704+
#ifdef VERIFIC_VHDL_SUPPORT
2705+
prev_1240 = Message::GetMessageType("VHDL-1240") ;
2706+
prev_1241 = Message::GetMessageType("VHDL-1241") ;
2707+
Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
2708+
Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
2709+
#endif
2710+
}
2711+
2712+
void restore_blackbox_msg_state()
2713+
{
2714+
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
2715+
Message::ClearMessageType("VERI-1063") ;
2716+
if (Message::GetMessageType("VERI-1063")!=prev_1063)
2717+
Message::SetMessageType("VERI-1063", prev_1063);
2718+
#endif
2719+
#ifdef VERIFIC_VHDL_SUPPORT
2720+
Message::ClearMessageType("VHDL-1240") ;
2721+
Message::ClearMessageType("VHDL-1241") ;
2722+
if (Message::GetMessageType("VHDL-1240")!=prev_1240)
2723+
Message::SetMessageType("VHDL-1240", prev_1240);
2724+
if (Message::GetMessageType("VHDL-1241")!=prev_1241)
2725+
Message::SetMessageType("VHDL-1241", prev_1241);
2726+
#endif
2727+
}
2728+
26912729
void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED)
26922730
{
26932731
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
2732+
save_blackbox_msg_state();
26942733
VerificExtensions::ElaborateAndRewrite(work, parameters);
26952734
verific_error_msg.clear();
2735+
restore_blackbox_msg_state();
26962736
#endif
26972737
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
26982738
if (!ppfile.empty())
@@ -2823,8 +2863,10 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
28232863

28242864
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
28252865
if (static_elaborate) {
2866+
save_blackbox_msg_state();
28262867
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters);
28272868
verific_error_msg.clear();
2869+
restore_blackbox_msg_state();
28282870
#endif
28292871
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
28302872
if (!ppfile.empty())
@@ -3290,10 +3332,8 @@ struct VerificPass : public Pass {
32903332
return filename;
32913333
}
32923334

3293-
#ifdef VERIFIC_VHDL_SUPPORT
3294-
msg_type_t prev_1240 ;
3295-
msg_type_t prev_1241 ;
32963335

3336+
#ifdef VERIFIC_VHDL_SUPPORT
32973337
void add_units_to_map(Map &map, std::string work, bool flag_lib)
32983338
{
32993339
MapIter mi ;
@@ -3306,11 +3346,7 @@ struct VerificPass : public Pass {
33063346
map.Insert(unit,unit);
33073347
}
33083348
}
3309-
3310-
prev_1240 = Message::GetMessageType("VHDL-1240") ;
3311-
prev_1241 = Message::GetMessageType("VHDL-1241") ;
3312-
Message::SetMessageType("VHDL-1240", VERIFIC_INFO);
3313-
Message::SetMessageType("VHDL-1241", VERIFIC_INFO);
3349+
save_blackbox_msg_state();
33143350
}
33153351

33163352
void set_units_to_blackbox(Map &map, std::string work, bool flag_lib)
@@ -3325,17 +3361,10 @@ struct VerificPass : public Pass {
33253361
unit->SetCompileAsBlackbox();
33263362
}
33273363
}
3328-
Message::ClearMessageType("VHDL-1240") ;
3329-
Message::ClearMessageType("VHDL-1241") ;
3330-
if (Message::GetMessageType("VHDL-1240")!=prev_1240)
3331-
Message::SetMessageType("VHDL-1240", prev_1240);
3332-
if (Message::GetMessageType("VHDL-1241")!=prev_1241)
3333-
Message::SetMessageType("VHDL-1241", prev_1241);
3334-
3364+
restore_blackbox_msg_state();
33353365
}
33363366
#endif
33373367

3338-
msg_type_t prev_1063;
33393368
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
33403369
void add_modules_to_map(Map &map, std::string work, bool flag_lib)
33413370
{
@@ -3349,9 +3378,7 @@ struct VerificPass : public Pass {
33493378
map.Insert(veri_module,veri_module);
33503379
}
33513380
}
3352-
3353-
prev_1063 = Message::GetMessageType("VERI-1063") ;
3354-
Message::SetMessageType("VERI-1063", VERIFIC_INFO);
3381+
save_blackbox_msg_state();
33553382
}
33563383

33573384
void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib)
@@ -3366,9 +3393,6 @@ struct VerificPass : public Pass {
33663393
veri_module->SetCompileAsBlackbox();
33673394
}
33683395
}
3369-
Message::ClearMessageType("VERI-1063") ;
3370-
if (Message::GetMessageType("VERI-1063")!=prev_1063)
3371-
Message::SetMessageType("VERI-1063", prev_1063);
33723396
}
33733397
#endif
33743398

@@ -3424,7 +3448,6 @@ struct VerificPass : public Pass {
34243448
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
34253449
RuntimeFlags::SetVar("veri_preserve_comments", 1);
34263450
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
3427-
RuntimeFlags::SetVar("veri_create_empty_box", 1);
34283451

34293452
// Workaround for VIPER #13851
34303453
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

‎tests/verific/blackbox_empty.ys‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
verific -sv <<EOF
2+
module TEST_CELL(input clk, input a, input b, output reg c);
3+
parameter PATH = "DEFAULT";
4+
endmodule
5+
EOF
6+
7+
verific -sv <<EOF
8+
module top(input clk, input a, input b, output c, output d);
9+
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
10+
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
11+
endmodule
12+
EOF
13+
14+
verific -import top
15+
hierarchy -top top
16+
stat
17+
select -assert-count 2 t:TEST_CELL

‎tests/verific/blackbox_ql.ys‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
2+
3+
verific -sv <<EOF
4+
module top (
5+
input wire [19:0] a,
6+
input wire [17:0] b,
7+
output wire [37:0] z,
8+
input wire clk,
9+
input wire reset,
10+
input wire unsigned_a,
11+
input wire unsigned_b,
12+
input wire f_mode,
13+
input wire [2:0] output_select,
14+
input wire register_inputs
15+
);
16+
17+
// module instantiation
18+
QL_DSP2_MULT_REGIN_REGOUT #(
19+
.MODE_BITS(80'h1232324)
20+
) u1 (
21+
.a (a),
22+
.b (b),
23+
.z (z),
24+
.clk (clk),
25+
.reset (reset),
26+
27+
.unsigned_a (unsigned_a),
28+
.unsigned_b (unsigned_b),
29+
30+
.f_mode (f_mode),
31+
.output_select (output_select),
32+
.register_inputs (register_inputs)
33+
);
34+
endmodule
35+
36+
EOF
37+
38+
verific -import top
39+
hierarchy -top top
40+
synth_quicklogic -family qlf_k6n10f
41+
select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324

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