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yrabbitRavenslofty
yrabbit
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Gowin. Renaming inputs of the DCS primitive.
The dynamic clock selection (DCS) primitive has undergone changes with the release of the GW5A series—the CLK0,1,2,3 inputs are now CLKIN0,1,2,3, but only for GW5A series chips. There are no functional changes, only renaming. Here we are transferring the description of the DCS primitive from general to specialized files for each chip series. We have also fixed a bug in the generation script that caused the loss of primitive parameters. Fortunately, this only affected the analog-to-digital converter, which has not yet been implemented. Signed-off-by: YRabbit <[email protected]>
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‎techlibs/gowin/cells_sim.v‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1958,14 +1958,6 @@ parameter FREQ_DIV = 100;
19581958
parameter REGULATOR_EN = 1'b0;
19591959
endmodule
19601960

1961-
(* blackbox *)
1962-
module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
1963-
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
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input [3:0] CLKSEL;
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output CLKOUT;
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parameter DCS_MODE = "RISING";
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endmodule
1968-
19691961
(* blackbox *)
19701962
module EMCU (
19711963
input FCLK,

‎techlibs/gowin/cells_xtra.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ class State(Enum):
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'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
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'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
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'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
28-
'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU',
28+
'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'EMCU',
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# These are not planned for implementation
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'MUX2_MUX8', 'MUX2_MUX16', 'MUX2_MUX32', 'MUX4', 'MUX8', 'MUX16',
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'MUX32', 'DL', 'DLE', 'DLC', 'DLCE', 'DLP', 'DLPE', 'DLN', 'DLNE',
@@ -50,7 +50,7 @@ def xtract_cells_decl(dir, fout):
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fout.write('\n')
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if l.rstrip()[-1] != ';':
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state = State.IN_MODULE_MULTILINE
53-
elif l.startswith('parameter') and state == State.IN_MODULE:
53+
elif l.lstrip().startswith('parameter') and state == State.IN_MODULE:
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fout.write(l)
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if l.rstrip()[-1] == ',':
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state = State.IN_PARAMETER

‎techlibs/gowin/cells_xtra_gw1n.v‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1109,6 +1109,13 @@ parameter IDLE = 4'd0,
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RD_S2 = 4'd12;
11101110
endmodule
11111111

1112+
module DCS (...);
1113+
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
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input [3:0] CLKSEL;
1115+
output CLKOUT;
1116+
parameter DCS_MODE = "RISING";
1117+
endmodule
1118+
11121119
module DQCE (...);
11131120
input CLKIN;
11141121
input CE;

‎techlibs/gowin/cells_xtra_gw2a.v‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1082,6 +1082,11 @@ input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
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output DQSR90, DQSW0, DQSW270;
10831083
output [2:0] RPOINT, WPOINT;
10841084
output RVALID,RBURST, RFLAG, WFLAG;
1085+
parameter FIFO_MODE_SEL = 1'b0;
1086+
parameter RD_PNTR = 3'b000;
1087+
parameter DQS_MODE = "X1";
1088+
parameter HWL = "false";
1089+
parameter GSREN = "false";
10851090
endmodule
10861091

10871092
module DLLDLY (...);
@@ -1095,6 +1100,13 @@ parameter DLY_SIGN = 1'b0;
10951100
parameter DLY_ADJ = 0;
10961101
endmodule
10971102

1103+
module DCS (...);
1104+
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
1105+
input [3:0] CLKSEL;
1106+
output CLKOUT;
1107+
parameter DCS_MODE = "RISING";
1108+
endmodule
1109+
10981110
module DQCE (...);
10991111
input CLKIN;
11001112
input CE;

‎techlibs/gowin/cells_xtra_gw5a.v‎

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Original file line numberDiff line numberDiff line change
@@ -1143,6 +1143,13 @@ input CE;
11431143
output CLKOUT;
11441144
endmodule
11451145

1146+
module DCS (...);
1147+
input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE;
1148+
input [3:0] CLKSEL;
1149+
output CLKOUT;
1150+
parameter DCS_MODE = "RISING";
1151+
endmodule
1152+
11461153
module DDRDLL (...);
11471154
input CLKIN;
11481155
input STOP;
@@ -1714,18 +1721,94 @@ input LOAD;
17141721
endmodule
17151722

17161723
module ADCLRC (...);
1724+
parameter DYN_BKEN = "FALSE";
1725+
parameter BUF_SERDES_Q1_EN = 3'b000;
1726+
parameter BUF_BK2_EN = 6'b000000;
1727+
parameter BUF_BK3_EN = 6'b000000;
1728+
parameter BUF_BK4_EN = 6'b000000;
1729+
parameter BUF_BK5_EN = 6'b000000;
1730+
parameter BUF_BK10_EN = 5'b00000;
1731+
parameter BUF_BK11_EN = 5'b00000;
1732+
parameter CLK_SEL = 1'b0;
1733+
parameter PIOCLK_SEL = 1'b0;
1734+
parameter VSEN_CTL = 3'b000;
1735+
parameter VSEN_CTL_SEL = 1'b0;
1736+
parameter ADC_MODE = 1'b0;
1737+
parameter DIV_CTL = 2'd0;
1738+
parameter SAMPLE_CNT_SEL = 3'd4;
1739+
parameter RATE_CHANGE_CTRL = 3'd4;
17171740
endmodule
17181741

17191742
module ADCULC (...);
1743+
parameter DYN_BKEN = "FALSE";
1744+
parameter BUF_VCC_EN = 1'b0;
1745+
parameter BUF_VCCM_EN = 1'b0;
1746+
parameter BUF_MIPI_M0_EN = 3'b000;
1747+
parameter BUF_MIPI_M1_EN = 3'b000;
1748+
parameter BUF_SERDES_Q0_EN = 3'b000;
1749+
parameter BUF_BK6_EN = 6'b000000;
1750+
parameter BUF_BK7_EN = 6'b000000;
1751+
parameter CLK_SEL = 1'b0;
1752+
parameter PIOCLK_SEL = 1'b0;
1753+
parameter VSEN_CTL = 3'b000;
1754+
parameter VSEN_CTL_SEL = 1'b0;
1755+
parameter ADC_MODE = 1'b0;
1756+
parameter DIV_CTL = 2'd0;
1757+
parameter SAMPLE_CNT_SEL = 3'd4;
1758+
parameter RATE_CHANGE_CTRL = 3'd4;
17201759
endmodule
17211760

17221761
module ADC (...);
1762+
parameter CLK_SEL = 1'b0;
1763+
parameter DIV_CTL = 2'd0;
1764+
parameter BUF_EN = 12'b000000000000;
1765+
parameter BUF_BK0_VREF_EN = 1'b0;
1766+
parameter BUF_BK1_VREF_EN = 1'b0;
1767+
parameter BUF_BK2_VREF_EN = 1'b0;
1768+
parameter BUF_BK3_VREF_EN = 1'b0;
1769+
parameter BUF_BK4_VREF_EN = 1'b0;
1770+
parameter BUF_BK5_VREF_EN = 1'b0;
1771+
parameter BUF_BK6_VREF_EN = 1'b0;
1772+
parameter BUF_BK7_VREF_EN = 1'b0;
1773+
parameter CSR_ADC_MODE = 1'b1;
1774+
parameter CSR_VSEN_CTRL = 3'd0;
1775+
parameter CSR_SAMPLE_CNT_SEL = 3'd4;
1776+
parameter CSR_RATE_CHANGE_CTRL = 3'd4;
1777+
parameter CSR_FSCAL = 10'd730;
1778+
parameter CSR_OFFSET = -12'd1180;
17231779
endmodule
17241780

17251781
module ADC_SAR (...);
1782+
parameter BUF_EN = 29'b0;
1783+
parameter CLK_SEL = 1'b1;
1784+
parameter DIV_CTL = 2'd2;
1785+
parameter ADC_EN_SEL = 1'b0;
1786+
parameter PHASE_SEL = 1'b0;
1787+
parameter CSR_ADC_MODE = 1'b1;
1788+
parameter CSR_VSEN_CTRL = 3'd0;
1789+
parameter CSR_SAMPLE_CNT_SEL = 3'd4;
1790+
parameter CSR_RATE_CHANGE_CTRL = 3'd4;
1791+
parameter CSR_FSCAL = 10'd730;
1792+
parameter CSR_OFFSET = -12'd1180;
1793+
parameter ADC_CLK_DIV = 2'b00;
1794+
parameter ADC_CLKDIV_EN = 1'b0;
1795+
parameter CLK_SRC_SEL = 1'b1;
1796+
parameter VREF_BUF_EN = 1'b1;
1797+
parameter COUNT_LEN = 5'b10100;
1798+
parameter DAC_SAMPLE_END = 5'b10010;
1799+
parameter DAC_SAMPLE_START = 5'b01101;
1800+
parameter SH_SAMPLE_END = 5'b01011;
1801+
parameter SH_SAMPLE_START = 5'b00001;
1802+
parameter AUTO_CHOP_EN = 1'b0;
1803+
parameter CHOP_CLK_DIV = 4'b0;
17261804
endmodule
17271805

17281806
module LICD (...);
1807+
parameter STAGE_NUM = 2'b00;
1808+
parameter ENCDEC_NUM = 2'b00;
1809+
parameter CODE_WIDTH = 2'b00;
1810+
parameter INTERLEAVE_EN = 3'b000;
1811+
parameter INTERLEAVE_MODE = 3'b000;
17291812
endmodule
17301813

17311814
module MIPI_DPHY (...);
@@ -2456,6 +2539,7 @@ parameter EQ_ZLD_LN2 = 4'b1000;
24562539
endmodule
24572540

24582541
module GTR12_QUAD (...);
2542+
parameter POSITION = "Q0";
24592543
endmodule
24602544

24612545
module GTR12_UPAR (...);

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