display logic depth and logic path

[shengqilong]

How to get the maximum logic depth and longest logic path after synthesis ？

[Ravenslofty]

ltp is longest topological path of logic by depth; sta is static timing analysis (although one would first need to re-read the simulation library to include the timing arcs)

[shengqilong]

The length displayed by ltp is very different from the length displayed after cell mapping，If cmos_cells.lib do not contain any timing information sta will not display the logical depth