interface modports as module ports

[ldoolitt]

One SystemVerilog idiom that I've seen in a couple of in-house projects uses interface modports to enforce something api-like, using not the whole interface but rather an interface modport as the port to a module.
I've tried to distill that to a small but complete and halfway-meaningful example:

interface bound;
   parameter WIDTH = 4;
   wire clk;
   wire [WIDTH-1:0] data;
   modport send(output clk, data);
   modport recv(input clk, data);
endinterface

module chip(input clk, input [2:0] sel, output led);
   bound #(.WIDTH(10)) b();
   counter c(.clk(clk), .send(b.send));
   select s(.recv(b.recv), .sel(sel), .led(led));
endmodule

module counter(input clk, bound.send send);
   reg [9:0] count=0;
   always @(posedge clk) count <= count+1;
   assign send.clk = clk;
   assign send.data = count;
endmodule

module select(bound.recv recv, input [2:0] sel, output led);
   wire clk = recv.clk;
   reg [2:0] sel_d=0;
   wire [7:0] sub_data = recv.data[9:2];
   reg muxo=0;
   always @(posedge clk) begin
      sel_d <= sel;
      muxo <= sub_data[sel_d];
   end
   assign led = muxo;
endmodule

This doesn't crash yosys, but the messages coming out make it pretty clear yosys doesn't understand or fully support this construction. Yosys-0.39 says

yosys> read_verilog -sv submodport.sv 
1. Executing Verilog-2005 frontend: submodport.sv
Parsing SystemVerilog input from `submodport.sv' to AST representation.
Generating RTLIL representation for module `\bound'.
Generating RTLIL representation for module `\chip'.
submodport.sv:11: Warning: Identifier `\b.send' is implicitly declared.
submodport.sv:12: Warning: Identifier `\b.recv' is implicitly declared.
Generating RTLIL representation for module `\counter'.
submodport.sv:18: Warning: Identifier `\send.clk' is implicitly declared.
submodport.sv:19: Warning: Identifier `\send.data' is implicitly declared.
Generating RTLIL representation for module `\select'.
submodport.sv:23: Warning: Identifier `\recv.clk' is implicitly declared.
submodport.sv:25: Warning: Identifier `\recv.data' is implicitly declared.
submodport.sv:25: Warning: Range select [9:2] out of bounds on signal `\recv.data': Setting all 8 result bits to undef.
Successfully finished Verilog frontend.

Is there a trick for writing this intent in a yosys-compatible way?
What vocabulary should I use talking about this idiom?
Is there hope to get support for it added to yosys?
Do other people/groups/projects do anything like this?
Etc.

[keithpenney]

I can confirm that Vivado 2022.1 handles the above example without even a warning (at least in simulation).