Outputs differ before and after synthesis.

[Noah-S-E]

Version

Yosys 0.39+165

On which OS did this happen?

Linux

Reproduction Steps

Hello, the outputs before and after synthesis are inconsistent when performing bitwise operations on signed numbers in Verilog using Yosys.

Given my original design, when the input sig_external_input is 6'b110011, the for loop should execute, and the if condition should be true, resulting in the output out_sig_main being 01. However, simulation results show that the original design outputs 00, while the synthesized design outputs 01.

module top (
    output wire [1:0] out_sig_main,   // primary output
    input  wire       clk_input_main, // clock
    input  wire signed [5:0] sig_external_input
);

    // Internal registers with overly verbose names and explicit signedness
    reg signed [1:0] reg_state_holder_alpha = (2'sb00);
    reg signed [6:0] loop_counter_variable_gamma = (7'sb0000000);

    // Extra wire that just forwards reg_state_holder_alpha for no reason
    wire [1:0] temp_forward_path_beta;
    assign temp_forward_path_beta = reg_state_holder_alpha;

    // Output mapping with redundant concatenation and slicing
    assign out_sig_main = { temp_forward_path_beta[1:0] };

    // Main clocked process
    always @(posedge clk_input_main) begin
        // Loop with excessive parentheses and verbose constants
        for (loop_counter_variable_gamma = (7'sb0000000);
             (loop_counter_variable_gamma < (7'sb0000001));
             loop_counter_variable_gamma = (loop_counter_variable_gamma + (7'sb0000001))) begin

            // Multi-level conditional using ternary operator and reduction
            if ( (^(loop_counter_variable_gamma + sig_external_input)) ? 
                 (loop_counter_variable_gamma) : 
                 (sig_external_input) ) begin

                // Extra nested begin-end for no reason
                begin
                    reg_state_holder_alpha = (2'sb01);
                end
            end
            else begin
                // Pointless "do nothing" assignment
                reg_state_holder_alpha = reg_state_holder_alpha;
            end
        end
    end

endmodule

The testbench is as follows：

`include "rtl.v"

module testbench;

  reg clk;
  reg signed [5:0] wire1;
  wire [1:0] y;


  top uut (
    .y(y),
    .clk(clk),
    .wire1(wire1)
  );


  initial begin
    clk = 0;
    forever #5 clk = ~clk; 
  end


  initial begin
 
    wire1 = 6'b110011;

 
    #10;
    $display("At time %t, y = %b", $time, y);

 
    #20;
    $finish;
  end
endmodule

Expected Behavior

output inconsistent

Actual Behavior

Inconsistent output before and after synthesis